Volume 2A Instruction Set Reference A-M (794101), страница 85
Текст из файла (страница 85)
In non-64-bitmode, only 32-bit (EDI) and 16-bit (DI) address sizes are supported.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionCopies the data from the I/O port specified with the source operand (secondoperand) to the destination operand (first operand). The source operand is an I/Oport address (from 0 to 65,535) that is read from the DX register. The destinationoperand is a memory location, the address of which is read from either the ES:DI,ES:EDI or the RDI registers (depending on the address-size attribute of the instruc-INS/INSB/INSW/INSD—Input from Port to StringVol.
2A 3-525INSTRUCTION SET REFERENCE, A-Mtion, 16, 32 or 64, respectively). (The ES segment cannot be overridden with asegment override prefix.) The size of the I/O port being accessed (that is, the size ofthe source and destination operands) is determined by the opcode for an 8-bit I/Oport or by the operand-size attribute of the instruction for a 16- or 32-bit I/O port.At the assembly-code level, two forms of this instruction are allowed: the “explicitoperands” form and the “no-operands” form.
The explicit-operands form (specifiedwith the INS mnemonic) allows the source and destination operands to be specifiedexplicitly. Here, the source operand must be “DX,” and the destination operandshould be a symbol that indicates the size of the I/O port and the destinationaddress. This explicit-operands form is provided to allow documentation; however,note that the documentation provided by this form can be misleading. That is, thedestination operand symbol must specify the correct type (size) of the operand(byte, word, or doubleword), but it does not have to specify the correct location.The location is always specified by the ES:(E)DI registers, which must be loadedcorrectly before the INS instruction is executed.The no-operands form provides “short forms” of the byte, word, and doublewordversions of the INS instructions.
Here also DX is assumed by the processor to be thesource operand and ES:(E)DI is assumed to be the destination operand. The size ofthe I/O port is specified with the choice of mnemonic: INSB (byte), INSW (word), orINSD (doubleword).After the byte, word, or doubleword is transfer from the I/O port to the memory location, the DI/EDI/RDI register is incremented or decremented automatically accordingto the setting of the DF flag in the EFLAGS register.
(If the DF flag is 0, the (E)DIregister is incremented; if the DF flag is 1, the (E)DI register is decremented.) The(E)DI register is incremented or decremented by 1 for byte operations, by 2 for wordoperations, or by 4 for doubleword operations.The INS, INSB, INSW, and INSD instructions can be preceded by the REP prefix forblock input of ECX bytes, words, or doublewords. See “REP/REPE/REPZ/REPNE/REPNZ—Repeat String Operation Prefix” in Chapter 4 of the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 2B, for a description of theREP prefix.These instructions are only useful for accessing I/O ports located in the processor’sI/O address space.
See Chapter 13, “Input/Output,” in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for more information onaccessing I/O ports in the I/O address space.In 64-bit mode, default address size is 64 bits, 32 bit address size is supported usingthe prefix 67H. The address of the memory destination is specified by RDI or EDI.16-bit address size is not supported in 64-bit mode. The operand size is notpromoted.OperationIF ((PE = 1) and ((CPL > IOPL) or (VM = 1)))THEN (* Protected mode with CPL > IOPL or virtual-8086 mode *)3-526 Vol. 2AINS/INSB/INSW/INSD—Input from Port to StringINSTRUCTION SET REFERENCE, A-MIF (Any I/O Permission Bit for I/O port being accessed = 1)THEN (* I/O operation is not allowed *)#GP(0);ELSE (* I/O operation is allowed *)DEST ← SRC; (* Read from I/O port *)FI;ELSE (Real Mode or Protected Mode with CPL IOPL *)DEST ← SRC; (* Read from I/O port *)FI;Non-64-bit Mode:IF (Byte transfer)THEN IF DF = 0THEN (E)DI ← (E)DI + 1;ELSE (E)DI ← (E)DI – 1; FI;ELSE IF (Word transfer)THEN IF DF = 0THEN (E)DI ← (E)DI + 2;ELSE (E)DI ← (E)DI – 2; FI;ELSE (* Doubleword transfer *)THEN IF DF = 0THEN (E)DI ← (E)DI + 4;ELSE (E)DI ← (E)DI – 4; FI;FI;FI;FI64-bit Mode:IF (Byte transfer)THEN IF DF = 0THEN (E|R)DI ← (E|R)DI + 1;ELSE (E|R)DI ← (E|R)DI – 1; FI;ELSE IF (Word transfer)THEN IF DF = 0THEN (E)DI ← (E)DI + 2;ELSE (E)DI ← (E)DI – 2; FI;ELSE (* Doubleword transfer *)THEN IF DF = 0THEN (E|R)DI ← (E|R)DI + 4;ELSE (E|R)DI ← (E|R)DI – 4; FI;FI;FI;INS/INSB/INSW/INSD—Input from Port to StringVol.
2A 3-527INSTRUCTION SET REFERENCE, A-MFlags AffectedNone.Protected Mode Exceptions#GP(0)If the CPL is greater than (has less privilege) the I/O privilegelevel (IOPL) and any of the corresponding I/O permission bits inTSS for the I/O port being accessed is 1.If the destination is located in a non-writable segment.If an illegal memory operand effective address in the ESsegments is given.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If any of the I/O permission bits in the TSS for the I/O port beingaccessed is 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the CPL is greater than (has less privilege) the I/O privilegelevel (IOPL) and any of the corresponding I/O permission bits inTSS for the I/O port being accessed is 1.If the memory address is in a non-canonical form.3-528 Vol.
2AINS/INSB/INSW/INSD—Input from Port to StringINSTRUCTION SET REFERENCE, A-M#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.INS/INSB/INSW/INSD—Input from Port to StringVol. 2A 3-529INSTRUCTION SET REFERENCE, A-MINSERTPS — Insert Packed Single Precision Floating-Point ValueOpcodeInstructionOp/En66 0F 3A 21 /ribINSERTPS xmm1, Axmm2/m32, imm864-BitModeCompat/ DescriptionLeg ModeValidValidInsert a single precisionfloating-point valueselected by imm8 fromxmm2/m32 into xmm1 atthe specified destinationelement specified by imm8and zero out destinationelements in xmm1 asindicated in imm8.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)imm8NADescriptionInsert a single-precision floating-point value from the source operand (secondoperand) into a specified location in the destination register operand (first operand)and selectively zero out the data elements in the destination according to the maskfield in the immediate byte (third operand).
The source operand can be a memorylocation (32 bits) or an XMM register.The immediate byte provides three fields:COUNT_S: The value of Imm8[7:6] selects the dword element from the sourceregister; it is 0 if the source is a memory operand.COUNT_D: The value of Imm8[5:4] selects the target dword element in the destination register.ZMASK: Each bit of Imm8[3:0] selects a dword element in the destination register tobe written with 0.0 if set to 1.OperationIF (SRC == REG) THEN COUNT_S Å imm8[7:6];ELSE COUNT_S Å 0; FI;COUNT_D Å imm8[5:4];ZMASK Å imm8[3:0];CASE (COUNT_S) OF0: TMP Å SRC[31:0];1: TMP Å SRC[63:32];3-530 Vol. 2AINSERTPS — Insert Packed Single Precision Floating-Point ValueINSTRUCTION SET REFERENCE, A-M2:3:TMP Å SRC[95:64];TMP Å SRC[127:96];CASE (COUNT_D) OF0: TMP2[31:0] Å TMP;TMP2[127:32] Å DEST[127:32];1: TMP2[63:32] Å TMP;TMP2[31:0] Å DEST[31:0];TMP2[127:64] Å DEST[127:64];2: TMP2[95:64] Å TMP;TMP2[63:0] Å DEST[63:0];TMP2[127:96] Å DEST[127:96];3: TMP2[127:96] Å TMP;TMP2[95:0] Å DEST[95:0];IF (ZMASK[0] == 1) THEN DEST[31:0] Å 00000000H;ELSE DEST[31:0] Å TMP2[31:0];IF (ZMASK[1] == 1) THEN DEST[63:32] Å 00000000H;ELSE DEST[63:32] Å TMP2[63:32];IF (ZMASK[2] == 1) THEN DEST[95:64] Å 00000000H;ELSE DEST[95:64] Å TMP2[95:64];IF (ZMASK[3] == 1) THEN DEST[127:96] Å 00000000H;ELSE DEST[127:96] Å TMP2[127:96];FI;FI;FI;FI;Intel C/C++ Compiler Intrinsic EquivalentINSERTPS__m128 _mm_insert_ps(__m128 dst, __m128 src, const int ndx);SIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS, or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.INSERTPS — Insert Packed Single Precision Floating-Point ValueVol.
2A 3-531INSTRUCTION SET REFERENCE, A-M#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real Mode Exceptions#GP(0)if any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in Protected Mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#PF(fault-code)For a page fault.#NMIf TS in CR0 is set.#UDIf EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag ECX.SSE4_1 is 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.#AC(0)3-532 Vol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
