Volume 2A Instruction Set Reference A-M (794101), страница 75
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If the value being storedis too large for the destination format, a numeric overflow exception (#O) is generated and, if the exception is unmasked, no value is stored in the destination operand.If the value being stored is a denormal value, the denormal exception (#D) is notgenerated. This condition is simply signaled as a numeric underflow exception (#U)condition.If the value being stored is ±0, ±∞, or a NaN, the least-significant bits of the significand and the exponent are truncated to fit the destination format. This operationpreserves the value’s identity as a 0, ∞, or NaN.FST/FSTP—Store Floating Point ValueVol.
2A 3-443INSTRUCTION SET REFERENCE, A-MIf the destination operand is a non-empty register, the invalid-operation exception isnot generated.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationDEST ← ST(0);IF Instruction = FSTPTHENPopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Indicates rounding direction of if the floating-point inexactexception (#P) is generated: 0 ← not roundup; 1 ← roundup.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value or unsupported format. Doesnot occur if the source operand is in double extended-precisionfloating-point format.#UResult is too small for the destination format.#OResult is too large for the destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-444 Vol.
2AFST/FSTP—Store Floating Point ValueINSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.FST/FSTP—Store Floating Point ValueVol.
2A 3-445INSTRUCTION SET REFERENCE, A-MFSTCW/FNSTCW—Store x87 FPU Control WordOpcodeInstruction64-BitModeCompat/Leg ModeDescription9B D9 /7FSTCW m2byteValidValidStore FPU control word to m2byteafter checking for pending unmaskedfloating-point exceptions.D9 /7FNSTCW* m2byteValidValidStore FPU control word to m2bytewithout checking for pendingunmasked floating-point exceptions.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionStores the current value of the FPU control word at the specified destination inmemory.
The FSTCW instruction checks for and handles pending unmasked floatingpoint exceptions before storing the control word; the FNSTCW instruction does not.The assembler issues two instructions for the FSTCW instruction (an FWAIT instruction followed by an FNSTCW instruction), and the processor executes each of theseinstructions in separately. If an exception is generated for either of these instructions, the save EIP points to the instruction that caused the exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.IA-32 Architecture CompatibilityWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it ispossible (under unusual circumstances) for an FNSTCW instruction to be interruptedprior to being executed to handle a pending FPU exception.
See the section titled“No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for adescription of these circumstances. An FNSTCW instruction cannot be interrupted inthis way on a Pentium 4, Intel Xeon, or P6 family processor.OperationDEST ← FPUControlWord;FPU Flags AffectedThe C0, C1, C2, and C3 flags are undefined.Floating-Point ExceptionsNone.3-446 Vol. 2AFSTCW/FNSTCW—Store x87 FPU Control WordINSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.FSTCW/FNSTCW—Store x87 FPU Control WordVol.
2A 3-447INSTRUCTION SET REFERENCE, A-M#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-448 Vol. 2AFSTCW/FNSTCW—Store x87 FPU Control WordINSTRUCTION SET REFERENCE, A-MFSTENV/FNSTENV—Store x87 FPU EnvironmentOpcodeInstruction9B D9 /6D9 /664-BitModeCompat/Leg ModeDescriptionFSTENV m14/28byte ValidValidStore FPU environment to m14byteor m28byte after checking forpending unmasked floating-pointexceptions. Then mask all floatingpoint exceptions.FNSTENV*m14/28byteValidStore FPU environment to m14byteor m28byte without checking forpending unmasked floating-pointexceptions.
Then mask all floatingpoint exceptions.ValidNOTES:* See IA-32 Architecture Compatibility section below.DescriptionSaves the current FPU operating environment at the memory location specified withthe destination operand, and then masks all floating-point exceptions. The FPU operating environment consists of the FPU control word, status word, tag word, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 in the Intel® 64and IA-32 Architectures Software Developer’s Manual, Volume 1, show the layout inmemory of the stored environment, depending on the operating mode of theprocessor (protected or real) and the current operand-size attribute (16-bit or32-bit). In virtual-8086 mode, the real mode layouts are used.The FSTENV instruction checks for and handles any pending unmasked floating-pointexceptions before storing the FPU environment; the FNSTENV instruction doesnot.
The saved image reflects the state of the FPU after all floating-point instructionspreceding the FSTENV/FNSTENV instruction in the instruction stream have beenexecuted.These instructions are often used by exception handlers because they provide accessto the FPU instruction and data pointers. The environment is typically saved in thestack.
Masking all exceptions after saving the environment prevents floating-pointexceptions from interrupting the exception handler.The assembler issues two instructions for the FSTENV instruction (an FWAIT instruction followed by an FNSTENV instruction), and the processor executes each of theseinstructions separately. If an exception is generated for either of these instructions,the save EIP points to the instruction that caused the exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.FSTENV/FNSTENV—Store x87 FPU EnvironmentVol. 2A 3-449INSTRUCTION SET REFERENCE, A-MIA-32 Architecture CompatibilityWhen operating a Pentium or Intel486 processor in MS-DOS compatibility mode, it ispossible (under unusual circumstances) for an FNSTENV instruction to be interruptedprior to being executed to handle a pending FPU exception.
See the section titled“No-Wait FPU Instructions Can Get FPU Interrupt in Window” in Appendix D of theIntel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for adescription of these circumstances. An FNSTENV instruction cannot be interrupted inthis way on a Pentium 4, Intel Xeon, or P6 family processor.OperationDEST[FPUControlWord] ← FPUControlWord;DEST[FPUStatusWord] ← FPUStatusWord;DEST[FPUTagWord] ← FPUTagWord;DEST[FPUDataPointer] ← FPUDataPointer;DEST[FPUInstructionPointer] ← FPUInstructionPointer;DEST[FPULastInstructionOpcode] ← FPULastInstructionOpcode;FPU Flags AffectedThe C0, C1, C2, and C3 are undefined.Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GP3-450 Vol.
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