Volume 2A Instruction Set Reference A-M (794101), страница 70
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In virtual-8086 mode, the real mode layouts are used.The FLDENV instruction should be executed in the same operating mode as the corresponding FSTENV/FNSTENV instruction.If one or more unmasked exception flags are set in the new FPU status word, afloating-point exception will be generated upon execution of the next floating-pointinstruction (except for the no-wait floating-point instructions, see the section titled“Software Exception Handling” in Chapter 8 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1). To avoid generating exceptions whenloading a new environment, clear all the exception flags in the FPU status word thatis being loaded.If a page or limit fault occurs during the execution of this instruction, the state of thex87 FPU registers as seen by the fault handler may be different than the state beingloaded from memory.
In such situations, the fault handler should ignore the status ofthe x87 FPU registers, handle the fault, and return. The FLDENV instruction will thencomplete the loading of the x87 FPU registers with no resulting context inconsistency.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationFPUControlWord ← SRC[FPUControlWord];FPUStatusWord ← SRC[FPUStatusWord];FPUTagWord ← SRC[FPUTagWord];FPUDataPointer ← SRC[FPUDataPointer];FPUInstructionPointer ← SRC[FPUInstructionPointer];FPULastInstructionOpcode ← SRC[FPULastInstructionOpcode];FLDENV—Load x87 FPU EnvironmentVol. 2A 3-405INSTRUCTION SET REFERENCE, A-MFPU Flags AffectedThe C0, C1, C2, C3 flags are loaded.Floating-Point ExceptionsNone; however, if an unmasked exception is loaded in the status word, it is generatedupon execution of the next “waiting” floating-point instruction.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.3-406 Vol.
2AFLDENV—Load x87 FPU EnvironmentINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.FLDENV—Load x87 FPU EnvironmentVol.
2A 3-407INSTRUCTION SET REFERENCE, A-MFMUL/FMULP/FIMUL—MultiplyOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD8 /1FMUL m32fpValidValidMultiply ST(0) by m32fp and storeresult in ST(0).DC /1FMUL m64fpValidValidMultiply ST(0) by m64fp and storeresult in ST(0).D8 C8+iFMUL ST(0), ST(i)ValidValidMultiply ST(0) by ST(i) and store resultin ST(0).DC C8+iFMUL ST(i), ST(0)ValidValidMultiply ST(i) by ST(0) and store resultin ST(i).DE C8+iFMULP ST(i), ST(0)ValidValidMultiply ST(i) by ST(0), store result inST(i), and pop the register stack.DE C9FMULPValidValidMultiply ST(1) by ST(0), store result inST(1), and pop the register stack.DA /1FIMUL m32intValidValidMultiply ST(0) by m32int and storeresult in ST(0).DE /1FIMUL m16intValidValidMultiply ST(0) by m16int and storeresult in ST(0).DescriptionMultiplies the destination and source operands and stores the product in the destination location.
The destination operand is always an FPU data register; the sourceoperand can be an FPU data register or a memory location. Source operands inmemory can be in single-precision or double-precision floating-point format or inword or doubleword integer format.The no-operand version of the instruction multiplies the contents of the ST(1)register by the contents of the ST(0) register and stores the product in the ST(1)register.
The one-operand version multiplies the contents of the ST(0) register by thecontents of a memory location (either a floating point or an integer value) and storesthe product in the ST(0) register. The two-operand version, multiplies the contents ofthe ST(0) register by the contents of the ST(i) register, or vice versa, with the resultbeing stored in the register specified with the first operand (the destinationoperand).The FMULP instructions perform the additional operation of popping the FPU registerstack after storing the product. To pop the register stack, the processor marks theST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point multiply instructions always results in theregister stack being popped. In some assemblers, the mnemonic for this instructionis FMUL rather than FMULP.3-408 Vol.
2AFMUL/FMULP/FIMUL—MultiplyINSTRUCTION SET REFERENCE, A-MThe FIMUL instructions convert an integer source operand to double extendedprecision floating-point format before performing the multiplication.The sign of the result is always the exclusive-OR of the source signs, even if one ormore of the values being multiplied is 0 or ∞. When the source operand is an integer0, it is treated as a +0.The following table shows the results obtained when multiplying various classes ofnumbers, assuming that neither overflow nor underflow occurs.Table 3-34. FMUL/FMULP/FIMUL ResultsDESTSRC−•−F−0+0+F+•NaN−•+•+•**−•−•NaN−F+•+F+0−0−F−•NaN−I+•+F+0−0−F−•NaN−0*+0+0−0−0*NaN+0*−0−0+0+0*NaN+I−•−F−0+0+F+•NaN+F−•−F−0+0+F+•NaN+•−•−•**+•+•NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.I Means Integer.* Indicates invalid-arithmetic-operand (#IA) exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF Instruction = FIMULTHENDEST ← DEST ∗ ConvertToDoubleExtendedPrecisionFP(SRC);ELSE (* Source operand is floating-point value *)DEST ← DEST ∗ SRC;FI;IF Instruction = FMULPTHENPopRegisterStack;FI;FMUL/FMULP/FIMUL—MultiplyVol.
2A 3-409INSTRUCTION SET REFERENCE, A-MFPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.One operand is ±0 and the other is ±∞.#DSource operand is a denormal value.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.3-410 Vol.
2AFMUL/FMULP/FIMUL—MultiplyINSTRUCTION SET REFERENCE, A-M#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.FMUL/FMULP/FIMUL—MultiplyVol. 2A 3-411INSTRUCTION SET REFERENCE, A-MFNOP—No OperationOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 D0FNOPValidValidNo operation is performed.DescriptionPerforms no FPU operation.
This instruction takes up space in the instruction streambut does not affect the FPU or machine context, except the EIP register.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.FPU Flags AffectedC0, C1, C2, C3 undefined.Floating-Point ExceptionsNone.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-412 Vol.
2AFNOP—No OperationINSTRUCTION SET REFERENCE, A-MFPATAN—Partial ArctangentOpcode*Instruction64-BitModeCompat/Leg ModeDescriptionD9 F3FPATANValidValidReplace ST(1) with arctan(ST(1)/ST(0)) and popthe register stack.NOTES:* See IA-32 Architecture Compatibility section below.DescriptionComputes the arctangent of the source operand in register ST(1) divided by thesource operand in register ST(0), stores the result in ST(1), and pops the FPUregister stack.
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