Volume 2A Instruction Set Reference A-M (794101), страница 66
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The contents of the FPU data registers and tagregister are not affected.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF TOP = 0THEN TOP ← 7;ELSE TOP ← TOP – 1;FI;FPU Flags AffectedThe C1 flag is set to 0. The C0, C2, and C3 flags are undefined.Floating-Point ExceptionsNone.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.FDECSTP—Decrement Stack-Top PointerVol. 2A 3-371INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-372 Vol.
2AFDECSTP—Decrement Stack-Top PointerINSTRUCTION SET REFERENCE, A-MFDIV/FDIVP/FIDIV—DivideOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD8 /6FDIV m32fpValidValidDivide ST(0) by m32fp and storeresult in ST(0).DC /6FDIV m64fpValidValidDivide ST(0) by m64fp and storeresult in ST(0).D8 F0+iFDIV ST(0), ST(i)ValidValidDivide ST(0) by ST(i) and store resultin ST(0).DC F8+iFDIV ST(i), ST(0)ValidValidDivide ST(i) by ST(0) and store resultin ST(i).DE F8+iFDIVP ST(i), ST(0)ValidValidDivide ST(i) by ST(0), store result inST(i), and pop the register stack.DE F9FDIVPValidValidDivide ST(1) by ST(0), store result inST(1), and pop the register stack.DA /6FIDIV m32intValidValidDivide ST(0) by m32int and storeresult in ST(0).DE /6FIDIV m16intValidValidDivide ST(0) by m64int and storeresult in ST(0).DescriptionDivides the destination operand by the source operand and stores the result in thedestination location.
The destination operand (dividend) is always in an FPU register;the source operand (divisor) can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format,word or doubleword integer format.The no-operand version of the instruction divides the contents of the ST(1) registerby the contents of the ST(0) register. The one-operand version divides the contentsof the ST(0) register by the contents of a memory location (either a floating-point oran integer value). The two-operand version, divides the contents of the ST(0)register by the contents of the ST(i) register or vice versa.The FDIVP instructions perform the additional operation of popping the FPU registerstack after storing the result.
To pop the register stack, the processor marks theST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point divide instructions always results in the registerstack being popped. In some assemblers, the mnemonic for this instruction is FDIVrather than FDIVP.The FIDIV instructions convert an integer source operand to double extended-precision floating-point format before performing the division.
When the source operandis an integer 0, it is treated as a +0.FDIV/FDIVP/FIDIV—DivideVol. 2A 3-373INSTRUCTION SET REFERENCE, A-MIf an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if theexception is masked, an ∞ of the appropriate sign is stored in the destinationoperand.The following table shows the results obtained when dividing various classes ofnumbers, assuming that neither overflow nor underflow occurs.Table 3-29.
FDIV/FDIVP/FIDIV ResultsDESTSRC−•−F−0+0+F+•NaN−•*+0+0−0−0*NaN−F+•+F+0−0−F−•NaN−I+•+F+0−0−F−•NaN−0+•******−•NaN+0−•******+•NaN+I−•−F−0+0+F+•NaN+F−•−F−0+0+F+•NaN+•*−0−0+0+0*NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.I Means integer.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.** Indicates floating-point zero-divide (#Z) exception.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF SRC = 0THEN#Z;ELSEIF Instruction is FIDIVTHENDEST ← DEST / ConvertToDoubleExtendedPrecisionFP(SRC);ELSE (* Source operand is floating-point value *)DEST ← DEST / SRC;FI;FI;3-374 Vol. 2AFDIV/FDIVP/FIDIV—DivideINSTRUCTION SET REFERENCE, A-MIF Instruction = FDIVPTHENPopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.±∞ / ±∞; ±0 / ±0#DSource is a denormal value.#ZDEST / ±0, where DEST is not equal to ±0.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#UDIf the LOCK prefix is used.FDIV/FDIVP/FIDIV—DivideVol.
2A 3-375INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-376 Vol.
2AFDIV/FDIVP/FIDIV—DivideINSTRUCTION SET REFERENCE, A-MFDIVR/FDIVRP/FIDIVR—Reverse DivideOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD8 /7FDIVR m32fpValidValidDivide m32fp by ST(0) and store resultin ST(0).DC /7FDIVR m64fpValidValidDivide m64fp by ST(0) and store resultin ST(0).D8 F8+iFDIVR ST(0), ST(i)ValidValidDivide ST(i) by ST(0) and store result inST(0).DC F0+iFDIVR ST(i), ST(0)ValidValidDivide ST(0) by ST(i) and store result inST(i).DE F0+iFDIVRP ST(i), ST(0) ValidValidDivide ST(0) by ST(i), store result inST(i), and pop the register stack.DE F1FDIVRPValidValidDivide ST(0) by ST(1), store result inST(1), and pop the register stack.DA /7FIDIVR m32intValidValidDivide m32int by ST(0) and store resultin ST(0).DE /7FIDIVR m16intValidValidDivide m16int by ST(0) and store resultin ST(0).DescriptionDivides the source operand by the destination operand and stores the result in thedestination location.
The destination operand (divisor) is always in an FPU register;the source operand (dividend) can be a register or a memory location. Source operands in memory can be in single-precision or double-precision floating-point format,word or doubleword integer format.These instructions perform the reverse operations of the FDIV, FDIVP, and FIDIVinstructions. They are provided to support more efficient coding.The no-operand version of the instruction divides the contents of the ST(0) registerby the contents of the ST(1) register. The one-operand version divides the contentsof a memory location (either a floating-point or an integer value) by the contents ofthe ST(0) register.
The two-operand version, divides the contents of the ST(i)register by the contents of the ST(0) register or vice versa.The FDIVRP instructions perform the additional operation of popping the FPU registerstack after storing the result. To pop the register stack, the processor marks theST(0) register as empty and increments the stack pointer (TOP) by 1. The nooperand version of the floating-point divide instructions always results in the registerstack being popped. In some assemblers, the mnemonic for this instruction is FDIVRrather than FDIVRP.FDIVR/FDIVRP/FIDIVR—Reverse DivideVol. 2A 3-377INSTRUCTION SET REFERENCE, A-MThe FIDIVR instructions convert an integer source operand to double extended-precision floating-point format before performing the division.If an unmasked divide-by-zero exception (#Z) is generated, no result is stored; if theexception is masked, an ∞ of the appropriate sign is stored in the destinationoperand.The following table shows the results obtained when dividing various classes ofnumbers, assuming that neither overflow nor underflow occurs.Table 3-30.
FDIVR/FDIVRP/FIDIVR ResultsDEST−•−F−0+0+F+•NaN−•*+•+•−•−•*NaN−F+0+F****−F−0NaN−I+0+F****−F−0NaN−0+0+0**−0−0NaN+0−0−0**+0+0NaN+I−0−F****+F+0NaN+F−0−F****+F+0NaN+•*−•−•+•+•*NaNNaNNaNNaNNaNNaNNaNNaNNaNSRCNOTES:F Means finite floating-point value.I Means integer.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.** Indicates floating-point zero-divide (#Z) exception.When the source operand is an integer 0, it is treated as a +0. This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF DEST = 0THEN#Z;ELSEIF Instruction = FIDIVRTHENDEST ← ConvertToDoubleExtendedPrecisionFP(SRC) / DEST;ELSE (* Source operand is floating-point value *)3-378 Vol. 2AFDIVR/FDIVRP/FIDIVR—Reverse DivideINSTRUCTION SET REFERENCE, A-MDEST ← SRC / DEST;FI;FI;IF Instruction = FDIVRPTHENPopRegisterStack;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IAOperand is an SNaN value or unsupported format.±∞ / ±∞; ±0 / ±0#DSource is a denormal value.#ZSRC / ±0, where SRC is not equal to ±0.#UResult is too small for destination format.#OResult is too large for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.FDIVR/FDIVRP/FIDIVR—Reverse DivideVol.
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