Volume 2A Instruction Set Reference A-M (794101), страница 72
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The magnitude of theremainder is less than or equal to half the magnitude of the modulus, unless a partialremainder was computed (as described below).This instruction produces an exact result; the precision (inexact) exception does notoccur and the rounding control has no effect. The following table shows the resultsobtained when computing the remainder of various classes of numbers, assumingthat underflow does not occur.Table 3-37. FPREM1 ResultsST(1)ST(0)-•−F−0+0+F+•NaN-•******NaN−FST(0)±F or −0****± F or −0ST(0)NaN−0−0−0**−0-0NaN+0+0+0**+0+0NaN+FST(0)± F or + 0****± F or +0ST(0)NaN+•******NaNNaNNaNNaNNaNNaNNaNNaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.** Indicates floating-point zero-divide (#Z) exception.When the result is 0, its sign is the same as that of the dividend.
When the modulusis ∞, the result is equal to the value in ST(0).FPREM1—Partial RemainderVol. 2A 3-419INSTRUCTION SET REFERENCE, A-MThe FPREM1 instruction computes the remainder specified in IEEE Standard 754.This instruction operates differently from the FPREM instruction in the way that itrounds the quotient of ST(0) divided by ST(1) to an integer (see the “Operation”section below).Like the FPREM instruction, FPREM1 computes the remainder through iterativesubtraction, but can reduce the exponent of ST(0) by no more than 63 in one execution of the instruction. If the instruction succeeds in producing a remainder that isless than one half the modulus, the operation is complete and the C2 flag in the FPUstatus word is cleared.
Otherwise, C2 is set, and the result in ST(0) is called thepartial remainder. The exponent of the partial remainder will be less than the exponent of the original dividend by at least 32. Software can re-execute the instruction(using the partial remainder in ST(0) as the dividend) until C2 is cleared. (Note thatwhile executing such a remainder-computation loop, a higher-priority interruptingroutine that needs the FPU can force a context switch in-between the instructions inthe loop.)An important use of the FPREM1 instruction is to reduce the arguments of periodicfunctions. When reduction is complete, the instruction stores the three least-significant bits of the quotient in the C3, C1, and C0 flags of the FPU status word.
This information is important in argument reduction for the tangent function (using a modulusof π/4), because it locates the original angle in the correct one of eight sectors of theunit circle.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationD ← exponent(ST(0)) – exponent(ST(1));IF D < 64THENQ ← Integer(RoundTowardNearestInteger(ST(0) / ST(1)));ST(0) ← ST(0) – (ST(1) ∗ Q);C2 ← 0;C0, C3, C1 ← LeastSignificantBits(Q); (* Q2, Q1, Q0 *)ELSEC2 ← 1;N ← An implementation-dependent number between 32 and 63;QQ ← Integer(TruncateTowardZero((ST(0) / ST(1)) / 2(D − N)));ST(0) ← ST(0) – (ST(1) ∗ QQ ∗ 2(D − N));FI;FPU Flags AffectedC0Set to bit 2 (Q2) of the quotient.C1Set to 0 if stack underflow occurred; otherwise, set to leastsignificant bit of quotient (Q0).3-420 Vol.
2AFPREM1—Partial RemainderINSTRUCTION SET REFERENCE, A-MC2Set to 0 if reduction complete; set to 1 if incomplete.C3Set to bit 1 (Q1) of the quotient.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value, modulus (divisor) is 0, dividend is ∞, or unsupported format.#DSource operand is a denormal value.#UResult is too small for destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.FPREM1—Partial RemainderVol.
2A 3-421INSTRUCTION SET REFERENCE, A-MFPTAN—Partial TangentOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 F2FPTANValidValidReplace ST(0) with its tangent andpush 1 onto the FPU stack.DescriptionComputes the tangent of the source operand in register ST(0), stores the result inST(0), and pushes a 1.0 onto the FPU register stack. The source operand must begiven in radians and must be less than ±263.
The following table shows theunmasked results obtained when computing the partial tangent of various classes ofnumbers, assuming that underflow does not occur.Table 3-38. FPTAN ResultsST(0) SRCST(0) DEST-•*-F− F to + F−0-0+0+0+F− F to + F+•*NaNNaNNOTES:F Means finite floating-point value.* Indicates floating-point invalid-arithmetic-operand (#IA) exception.If the source operand is outside the acceptable range, the C2 flag in the FPU statusword is set, and the value in register ST(0) remains unchanged. The instruction doesnot raise an exception when the source operand is out of range. It is up to theprogram to check the C2 flag for out-of-range conditions.
Source values outside therange −263 to +263 can be reduced to the range of the instruction by subtracting anappropriate integer multiple of 2π or by using the FPREM instruction with a divisor of2π. See the section titled “Pi” in Chapter 8 of the Intel® 64 and IA-32 ArchitecturesSoftware Developer’s Manual, Volume 1, for a discussion of the proper value to usefor π in performing such reductions.The value 1.0 is pushed onto the register stack after the tangent has been computedto maintain compatibility with the Intel 8087 and Intel287 math coprocessors.
Thisoperation also simplifies the calculation of other trigonometric functions. Forinstance, the cotangent (which is the reciprocal of the tangent) can be computed byexecuting a FDIVR instruction after the FPTAN instruction.3-422 Vol. 2AFPTAN—Partial TangentINSTRUCTION SET REFERENCE, A-MThis instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationIF ST(0) < 263THENC2 ← 0;ST(0) ← tan(ST(0));TOP ← TOP − 1;ST(0) ← 1.0;ELSE (* Source operand is out-of-range *)C2 ← 1;FI;FPU Flags AffectedC1Set to 0 if stack underflow occurred; set to 1 if stack overflowoccurred.Set if result was rounded up; cleared otherwise.C2Set to 1 if outside range (−263 < source operand < +263); otherwise, set to 0.C0, C3Undefined.Floating-Point Exceptions#ISStack underflow or overflow occurred.#IASource operand is an SNaN value, ∞, or unsupported format.#DSource operand is a denormal value.#UResult is too small for destination format.#PValue cannot be represented exactly in destination format.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.FPTAN—Partial TangentVol.
2A 3-423INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-424 Vol. 2AFPTAN—Partial TangentINSTRUCTION SET REFERENCE, A-MFRNDINT—Round to IntegerOpcodeInstruction64-BitModeCompat/Leg ModeDescriptionD9 FCFRNDINTValidValidRound ST(0) to an integer.DescriptionRounds the source value in the ST(0) register to the nearest integral value,depending on the current rounding mode (setting of the RC field of the FPU controlword), and stores the result in ST(0).If the source value is ∞, the value is not changed.
If the source value is not an integralvalue, the floating-point inexact-result exception (#P) is generated.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationST(0) ← RoundToIntegralValue(ST(0));FPU Flags AffectedC1Set to 0 if stack underflow occurred.Set if result was rounded up; cleared otherwise.C0, C2, C3Undefined.Floating-Point Exceptions#ISStack underflow occurred.#IASource operand is an SNaN value or unsupported format.#DSource operand is a denormal value.#PSource operand is not an integral value.Protected Mode Exceptions#NMCR0.EM[bit 2] or CR0.TS[bit 3] = 1.#MFIf there is a pending x87 FPU exception.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as in protected mode.Virtual-8086 Mode ExceptionsSame exceptions as in protected mode.FRNDINT—Round to IntegerVol.
2A 3-425INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsSame exceptions as in protected mode.3-426 Vol. 2AFRNDINT—Round to IntegerINSTRUCTION SET REFERENCE, A-MFRSTOR—Restore x87 FPU StateOpcodeInstruction64-BitModeDD /4FRSTOR m94/108byte ValidCompat/Leg ModeDescriptionValidLoad FPU state fromm94byte or m108byte.DescriptionLoads the FPU state (operating environment and register stack) from the memoryarea specified with the source operand. This state data is typically written to thespecified memory location by a previous FSAVE/FNSAVE instruction.The FPU operating environment consists of the FPU control word, status word, tagword, instruction pointer, data pointer, and last opcode. Figures 8-9 through 8-12 inthe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, showthe layout in memory of the stored environment, depending on the operating modeof the processor (protected or real) and the current operand-size attribute (16-bit or32-bit).
In virtual-8086 mode, the real mode layouts are used. The contents of theFPU register stack are stored in the 80 bytes immediately following the operatingenvironment image.The FRSTOR instruction should be executed in the same operating mode as thecorresponding FSAVE/FNSAVE instruction.If one or more unmasked exception bits are set in the new FPU status word, afloating-point exception will be generated. To avoid raising exceptions when loadinga new operating environment, clear all the exception flags in the FPU status wordthat is being loaded.This instruction’s operation is the same in non-64-bit modes and 64-bit mode.OperationFPUControlWord ← SRC[FPUControlWord];FPUStatusWord ← SRC[FPUStatusWord];FPUTagWord ← SRC[FPUTagWord];FPUDataPointer ← SRC[FPUDataPointer];FPUInstructionPointer ← SRC[FPUInstructionPointer];FPULastInstructionOpcode ← SRC[FPULastInstructionOpcode];ST(0) ← SRC[ST(0)];ST(1) ← SRC[ST(1)];ST(2) ← SRC[ST(2)];ST(3) ← SRC[ST(3)];ST(4) ← SRC[ST(4)];ST(5) ← SRC[ST(5)];ST(6) ← SRC[ST(6)];FRSTOR—Restore x87 FPU StateVol.
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