Volume 2A Instruction Set Reference A-M (794101), страница 36
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Useof the REX.W prefix promotes this instruction (CDQE when promoted) to operate on64-bit operands. In which case, CDQE copies the sign (bit 31) of the doubleword inthe EAX register into the high 32 bits of RAX.OperationIF OperandSize = 16 (* Instruction = CBW *)THENAX ← SignExtend(AL);ELSE IF (OperandSize = 32, Instruction = CWDE)EAX ← SignExtend(AX); FI;ELSE (* 64-Bit Mode, OperandSize = 64, Instruction = CDQE*)RAX ← SignExtend(EAX);FI;Flags AffectedNone.CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to QuadwordVol. 2A 3-139INSTRUCTION SET REFERENCE, A-MExceptions (All Operating Modes)#UD3-140 Vol.
2AIf the LOCK prefix is used.CBW/CWDE/CDQE—Convert Byte to Word/Convert Word to Doubleword/Convert Doubleword to QuadwordINSTRUCTION SET REFERENCE, A-MCLC—Clear Carry FlagOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg ModeF8CLCAValidValidClear CF flag.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionClears the CF flag in the EFLAGS register. Operation is the same in all non-64-bitmodes and 64-bit mode.OperationCF ← 0;Flags AffectedThe CF flag is set to 0. The OF, ZF, SF, AF, and PF flags are unaffected.Exceptions (All Operating Modes)#UDCLC—Clear Carry FlagIf the LOCK prefix is used.Vol. 2A 3-141INSTRUCTION SET REFERENCE, A-MCLD—Clear Direction FlagOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg ModeFCCLDAValidValidClear DF flag.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionClears the DF flag in the EFLAGS register.
When the DF flag is set to 0, string operations increment the index registers (ESI and/or EDI). Operation is the same in allnon-64-bit modes and 64-bit mode.OperationDF ← 0;Flags AffectedThe DF flag is set to 0. The CF, OF, ZF, SF, AF, and PF flags are unaffected.Exceptions (All Operating Modes)#UD3-142 Vol. 2AIf the LOCK prefix is used.CLD—Clear Direction FlagINSTRUCTION SET REFERENCE, A-MCLFLUSH—Flush Cache LineOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F AE /7CLFLUSH m8AValidValidFlushes cache linecontaining m8.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (w)NANANADescriptionInvalidates the cache line that contains the linear address specified with the sourceoperand from all levels of the processor cache hierarchy (data and instruction). Theinvalidation is broadcast throughout the cache coherence domain.
If, at any level ofthe cache hierarchy, the line is inconsistent with memory (dirty) it is written tomemory before invalidation. The source operand is a byte memory location.The availability of CLFLUSH is indicated by the presence of the CPUID feature flagCLFSH (bit 19 of the EDX register, see “CPUID—CPU Identification” in this chapter).The aligned cache line size affected is also indicated with the CPUID instruction (bits8 through 15 of the EBX register when the initial value in the EAX register is 1).The memory attribute of the page containing the affected line has no effect on thebehavior of this instruction.
It should be noted that processors are free to speculatively fetch and cache data from system memory regions assigned a memory-typeallowing for speculative reads (such as, the WB, WC, and WT memory types).PREFETCHh instructions can be used to provide the processor with hints for this speculative behavior.
Because this speculative fetching can occur at any time and is nottied to instruction execution, the CLFLUSH instruction is not ordered with respect toPREFETCHh instructions or any of the speculative fetching mechanisms (that is, datacan be speculatively loaded into a cache line just before, during, or after the execution of a CLFLUSH instruction that references the cache line).CLFLUSH is only ordered by the MFENCE instruction. It is not guaranteed to beordered by any other fencing or serializing instructions or by another CLFLUSHinstruction. For example, software can use an MFENCE instruction to ensure thatprevious stores are included in the write-back.The CLFLUSH instruction can be used at all privilege levels and is subject to allpermission checking and faults associated with a byte load (and in addition, aCLFLUSH instruction is allowed to flush a linear address in an execute-only segment).Like a load, the CLFLUSH instruction sets the A bit but not the D bit in the pagetables.The CLFLUSH instruction was introduced with the SSE2 extensions; however,because it has its own CPUID feature flag, it can be implemented in IA-32 processorsCLFLUSH—Flush Cache LineVol.
2A 3-143INSTRUCTION SET REFERENCE, A-Mthat do not include the SSE2 extensions. Also, detecting the presence of the SSE2extensions with the CPUID instruction does not guarantee that the CLFLUSH instruction is implemented in the processor.CLFLUSH operation is the same in non-64-bit modes and 64-bit mode.OperationFlush_Cache_Line(SRC);Intel C/C++ Compiler Intrinsic EquivalentsCLFLUSHvoid _mm_clflush(void const *p)Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#UDIf CPUID.01H:EDX.CLFSH[bit 19] = 0.If the LOCK prefix is used.Real-Address Mode ExceptionsGP#UDIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.If CPUID.01H:EDX.CLFSH[bit 19] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.#UDIf CPUID.01H:EDX.CLFSH[bit 19] = 0.If the LOCK prefix is used.3-144 Vol.
2ACLFLUSH—Flush Cache LineINSTRUCTION SET REFERENCE, A-MCLI — Clear Interrupt FlagOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg ModeFACLIAValidValidClear interrupt flag;interrupts disabled wheninterrupt flag cleared.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionIf protected-mode virtual interrupts are not enabled, CLI clears the IF flag in theEFLAGS register.
No other flags are affected. Clearing the IF flag causes theprocessor to ignore maskable external interrupts. The IF flag and the CLI and STIinstruction have no affect on the generation of exceptions and NMI interrupts.When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than3; CLI clears the VIF flag in the EFLAGS register, leaving IF unaffected.
Table 3-6 indicates the action of the CLI instruction depending on the processor operating modeand the CPL/IOPL of the running program or procedure.CLI operation is the same in non-64-bit modes and 64-bit mode.Table 3-6. Decision Table for CLI ResultsPEVMIOPLCPLPVIVIPVMECLI Result0XXXXXXIF = 010≥ CPLXXXXIF = 010< CPL31XXVIF = 010< CPL<3XXXGP Fault10< CPLX0XXGP Fault113XXXXIF = 011<3XXX1VIF = 011<3XXX0GP FaultNOTES:* X = This setting has no impact.OperationIF PE = 0CLI — Clear Interrupt FlagVol. 2A 3-145INSTRUCTION SET REFERENCE, A-MTHENIF ← 0; (* Reset Interrupt Flag *)ELSEIF VM = 0;THENIF IOPL ≥ CPLTHENIF ← 0; (* Reset Interrupt Flag *)ELSEIF ((IOPL < CPL) and (CPL = 3) and (PVI = 1))THENVIF ← 0; (* Reset Virtual Interrupt Flag *)ELSE#GP(0);FI;FI;ELSE (* VM = 1 *)IF IOPL = 3THENIF ← 0; (* Reset Interrupt Flag *)ELSEIF (IOPL < 3) AND (VME = 1)THENVIF ← 0; (* Reset Virtual Interrupt Flag *)ELSE#GP(0);FI;FI;FI;FI;Flags AffectedIf protected-mode virtual interrupts are not enabled, IF is set to 0 if the CPL is equalto or less than the IOPL; otherwise, it is not affected.
The other flags in the EFLAGSregister are unaffected.When protected-mode virtual interrupts are enabled, CPL is 3, and IOPL is less than3; CLI clears the VIF flag in the EFLAGS register, leaving IF unaffected.Protected Mode Exceptions#GP(0)If the CPL is greater (has less privilege) than the IOPL of thecurrent program or procedure.#UDIf the LOCK prefix is used.3-146 Vol. 2ACLI — Clear Interrupt FlagINSTRUCTION SET REFERENCE, A-MReal-Address Mode Exceptions#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If the CPL is greater (has less privilege) than the IOPL of thecurrent program or procedure.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#GP(0)If the CPL is greater (has less privilege) than the IOPL of thecurrent program or procedure.#UDIf the LOCK prefix is used.CLI — Clear Interrupt FlagVol.
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