Volume 2A Instruction Set Reference A-M (794101), страница 31
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Thebit base operand can be a register or a memory location; the bit offset operand canbe a register or an immediate value:•If the bit base operand specifies a register, the instruction takes the modulo 16,32, or 64 of the bit offset operand (modulo size depends on the mode andregister size; 64-bit operands are available only in 64-bit mode).
This allows anybit position to be selected.•If the bit base operand specifies a memory location, the operand represents theaddress of the byte in memory that contains the bit base (bit 0 of the specifiedbyte) of the bit string. The range of the bit position that can be referenced by theoffset operand depends on the operand size.See also: Bit(BitBase, BitOffset) on page 3-11.Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memoryoperand.
See “BT—Bit Test” in this chapter for more information on this addressingmechanism.BTC—Bit Test and ComplementVol. 2A 3-111INSTRUCTION SET REFERENCE, A-MThis instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15).
Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationCF ← Bit(BitBase, BitOffset);Bit(BitBase, BitOffset) ← NOT Bit(BitBase, BitOffset);Flags AffectedThe CF flag contains the value of the selected bit before it is complemented. The ZFflag is unaffected. The OF, SF, AF, and PF flags are undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)3-112 Vol.
2AIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.BTC—Bit Test and ComplementINSTRUCTION SET REFERENCE, A-M#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.BTC—Bit Test and ComplementVol.
2A 3-113INSTRUCTION SET REFERENCE, A-MBTR—Bit Test and ResetOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F B3BTR r/m16, r16AValidValidStore selected bit in CF flagand clear.0F B3BTR r/m32, r32AValidValidStore selected bit in CF flagand clear.REX.W + 0F B3BTR r/m64, r64AValidN.E.Store selected bit in CF flagand clear.0F BA /6 ibBTR r/m16, imm8BValidValidStore selected bit in CF flagand clear.0F BA /6 ibBTR r/m32, imm8BValidValidStore selected bit in CF flagand clear.REX.W + 0F BA/6 ibBTR r/m64, imm8BValidN.E.Store selected bit in CF flagand clear.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)ModRM:reg (r)NANABModRM:r/m (r, w)imm8NANADescriptionSelects the bit in a bit string (specified with the first operand, called the bit base) atthe bit-position designated by the bit offset operand (second operand), stores thevalue of the bit in the CF flag, and clears the selected bit in the bit string to 0.
The bitbase operand can be a register or a memory location; the bit offset operand can be aregister or an immediate value:•If the bit base operand specifies a register, the instruction takes the modulo 16,32, or 64 of the bit offset operand (modulo size depends on the mode andregister size; 64-bit operands are available only in 64-bit mode). This allows anybit position to be selected.•If the bit base operand specifies a memory location, the operand represents theaddress of the byte in memory that contains the bit base (bit 0 of the specifiedbyte) of the bit string.
The range of the bit position that can be referenced by theoffset operand depends on the operand size.See also: Bit(BitBase, BitOffset) on page 3-11.Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memoryoperand. See “BT—Bit Test” in this chapter for more information on this addressingmechanism.3-114 Vol.
2ABTR—Bit Test and ResetINSTRUCTION SET REFERENCE, A-MThis instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15).
Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationCF ← Bit(BitBase, BitOffset);Bit(BitBase, BitOffset) ← 0;Flags AffectedThe CF flag contains the value of the selected bit before it is cleared. The ZF flag isunaffected. The OF, SF, AF, and PF flags are undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)BTR—Bit Test and ResetIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.Vol.
2A 3-115INSTRUCTION SET REFERENCE, A-M#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.3-116 Vol.
2ABTR—Bit Test and ResetINSTRUCTION SET REFERENCE, A-MBTS—Bit Test and SetOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F ABBTS r/m16, r16AValidValidStore selected bit in CF flagand set.0F ABBTS r/m32, r32AValidValidStore selected bit in CF flagand set.REX.W + 0F ABBTS r/m64, r64AValidN.E.Store selected bit in CF flagand set.0F BA /5 ibBTS r/m16, imm8BValidValidStore selected bit in CF flagand set.0F BA /5 ibBTS r/m32, imm8BValidValidStore selected bit in CF flagand set.REX.W + 0F BA/5 ibBTS r/m64, imm8BValidN.E.Store selected bit in CF flagand set.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)ModRM:reg (r)NANABModRM:r/m (r, w)imm8NANADescriptionSelects the bit in a bit string (specified with the first operand, called the bit base) atthe bit-position designated by the bit offset operand (second operand), stores thevalue of the bit in the CF flag, and sets the selected bit in the bit string to 1.
The bitbase operand can be a register or a memory location; the bit offset operand can be aregister or an immediate value:•If the bit base operand specifies a register, the instruction takes the modulo 16,32, or 64 of the bit offset operand (modulo size depends on the mode andregister size; 64-bit operands are available only in 64-bit mode). This allows anybit position to be selected.•If the bit base operand specifies a memory location, the operand represents theaddress of the byte in memory that contains the bit base (bit 0 of the specifiedbyte) of the bit string.
The range of the bit position that can be referenced by theoffset operand depends on the operand size.See also: Bit(BitBase, BitOffset) on page 3-11.Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memoryoperand. See “BT—Bit Test” in this chapter for more information on this addressingmechanism.BTS—Bit Test and SetVol. 2A 3-117INSTRUCTION SET REFERENCE, A-MThis instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, the instruction’s default operation size is 32 bits.
Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationCF ← Bit(BitBase, BitOffset);Bit(BitBase, BitOffset) ← 1;Flags AffectedThe CF flag contains the value of the selected bit before it is set. The ZF flag is unaffected. The OF, SF, AF, and PF flags are undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP3-118 Vol.
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