Volume 2A Instruction Set Reference A-M (794101), страница 27
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2A 3-77INSTRUCTION SET REFERENCE, A-MANDNPD—Bitwise Logical AND NOT of Packed Double-PrecisionFloating-Point ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 55 /rANDNPD xmm1,xmm2/m128AValidValidBitwise logical AND NOT ofxmm2/m128 and xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionInverts the bits of the two packed double-precision floating-point values in the destination operand (first operand), performs a bitwise logical AND of the two packeddouble-precision floating-point values in the source operand (second operand) andthe temporary inverted result, and stores the result in the destination operand.The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[127:0] ← (NOT(DEST[127:0])) BitwiseAND (SRC[127:0]);Intel C/C++ Compiler Intrinsic EquivalentANDNPD__m128d _mm_andnot_pd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.3-78 Vol.
2AANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.ANDNPD—Bitwise Logical AND NOT of Packed Double-Precision Floating-Point ValuesVol.
2A 3-79INSTRUCTION SET REFERENCE, A-MANDNPS—Bitwise Logical AND NOT of Packed Single-PrecisionFloating-Point ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F 55 /rANDNPS xmm1,xmm2/m128AValidValidBitwise logical AND NOT ofxmm2/m128 and xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionInverts the bits of the four packed single-precision floating-point values in the destination operand (first operand), performs a bitwise logical AND of the four packedsingle-precision floating-point values in the source operand (second operand) andthe temporary inverted result, and stores the result in the destination operand.The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[127:0] ← (NOT(DEST[127:0])) BitwiseAND (SRC[127:0]);Intel C/C++ Compiler Intrinsic EquivalentANDNPS__m128 _mm_andnot_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.3-80 Vol. 2AANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.ANDNPS—Bitwise Logical AND NOT of Packed Single-Precision Floating-Point ValuesVol.
2A 3-81INSTRUCTION SET REFERENCE, A-MARPL—Adjust RPL Field of Segment SelectorOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode63 /rARPL r/m16, r16AN. E.ValidAdjust RPL of r/m16 to notless than RPL of r16.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (w)ModRM:reg (r)NANADescriptionCompares the RPL fields of two segment selectors. The first operand (the destinationoperand) contains one segment selector and the second operand (source operand)contains the other. (The RPL field is located in bits 0 and 1 of each operand.) If theRPL field of the destination operand is less than the RPL field of the source operand,the ZF flag is set and the RPL field of the destination operand is increased to matchthat of the source operand.
Otherwise, the ZF flag is cleared and no change is madeto the destination operand. (The destination operand can be a word register or amemory location; the source operand must be a word register.)The ARPL instruction is provided for use by operating-system procedures (however, itcan also be used by applications). It is generally used to adjust the RPL of a segmentselector that has been passed to the operating system by an application program tomatch the privilege level of the application program. Here the segment selectorpassed to the operating system is placed in the destination operand and segmentselector for the application program’s code segment is placed in the source operand.(The RPL field in the source operand represents the privilege level of the applicationprogram.) Execution of the ARPL instruction then ensures that the RPL of thesegment selector received by the operating system is no lower (does not have ahigher privilege) than the privilege level of the application program (the segmentselector for the application program’s code segment can be read from the stackfollowing a procedure call).This instruction executes as described in compatibility mode and legacy mode.
It isnot encodable in 64-bit mode.See “Checking Caller Access Privileges” in Chapter 3, “Protected-Mode MemoryManagement,” of the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 3A, for more information about the use of this instruction.3-82 Vol. 2AARPL—Adjust RPL Field of Segment SelectorINSTRUCTION SET REFERENCE, A-MOperationIF 64-BIT MODETHENSee MOVSXD;ELSEIF DEST[RPL) < SRC[RPL)THENZF ← 1;DEST[RPL) ← SRC[RPL);ELSEZF ← 0;FI;FI;Flags AffectedThe ZF flag is set to 1 if the RPL field of the destination operand is less than that ofthe source operand; otherwise, it is set to 0.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#UDThe ARPL instruction is not recognized in real-address mode.If the LOCK prefix is used.Virtual-8086 Mode Exceptions#UDThe ARPL instruction is not recognized in virtual-8086 mode.If the LOCK prefix is used.ARPL—Adjust RPL Field of Segment SelectorVol.
2A 3-83INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode ExceptionsNot applicable.3-84 Vol. 2AARPL—Adjust RPL Field of Segment SelectorINSTRUCTION SET REFERENCE, A-MBLENDPD — Blend Packed Double Precision Floating-Point ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 3A 0D /ribBLENDPD xmm1,xmm2/m128,imm8AValidValidSelect packed DP-FP valuesfrom xmm1 andxmm2/m128 from maskspecified in imm8 and storethe values into xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)imm8NADescriptionPacked double-precision floating-point values from the source operand (secondoperand) are conditionally copied to the destination operand depending on the maskbits in the immediate operand.
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