Volume 2A Instruction Set Reference A-M (794101), страница 25
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The second source operand can be an XMM register or a 128-bitmemory location.OperationAESDECLASTSTATE ← SRC1;RoundKey ← SRC2;STATE ← InvShiftRows( STATE );STATE ← InvSubBytes( STATE );DEST[127:0] ← STATE XOR RoundKey;DEST[255:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentAESDECLAST __m128i _mm_aesdeclast (__m128i, __m128i)SIMD Floating-Point ExceptionsNoneAESDECLAST—Perform Last Round of an AES Decryption FlowVol. 2A 3-57INSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.3-58 Vol.
2AAESDECLAST—Perform Last Round of an AES Decryption FlowINSTRUCTION SET REFERENCE, A-M#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.AESDECLAST—Perform Last Round of an AES Decryption FlowVol.
2A 3-59INSTRUCTION SET REFERENCE, A-MAESENC—Perform One Round of an AES Encryption FlowOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 38 DC /rAESENC xmm1,xmm2/m128AValidValidPerform one round of anAES encryption flow, operating on a 128-bit data (state)from xmm1 with a 128-bitround key fromxmm2/m128.Instruction Operand EncodingOp/EnOperand 1Operand2Operand3Operand4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionThis instruction performs a single round of an AES encryption flow using a round keyfrom the second source operand, operating on 128-bit data (state) from the firstsource operand, and store the result in the destination operand.Use the AESENC instruction for all but the last encryption rounds. For the last encryption round, use the AESENCCLAST instruction.The first source operand and the destination operand are the same and must be anXMM register.
The second source operand can be an XMM register or a 128-bitmemory location.OperationAESENCSTATE ← SRC1;RoundKey ← SRC2;STATE ← ShiftRows( STATE );STATE ← SubBytes( STATE );STATE ← MixColumns( STATE );DEST[127:0] ← STATE XOR RoundKey;DEST[255:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentAESENC __m128i _mm_aesenc (__m128i, __m128i)3-60 Vol. 2AAESENC—Perform One Round of an AES Encryption FlowINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.AESENC—Perform One Round of an AES Encryption FlowVol.
2A 3-61INSTRUCTION SET REFERENCE, A-MIf memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.3-62 Vol. 2AAESENC—Perform One Round of an AES Encryption FlowINSTRUCTION SET REFERENCE, A-MAESENCLAST—Perform Last Round of an AES Encryption FlowOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 38 DD /rAESENCLASTxmm1,xmm2/m128AValidValidPerform the last round of anAES encryption flow, operating on a 128-bit data (state)from xmm1 with a 128-bitround key fromxmm2/m128.Instruction Operand EncodingOp/EnOperand 1Operand2Operand3Operand4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionThis instruction performs the last round of an AES encryption flow using a round keyfrom the second source operand, operating on 128-bit data (state) from the firstsource operand, and store the result in the destination operand.The first source operand and the destination operand are the same and must be anXMM register.
The second source operand can be an XMM register or a 128-bitmemory location.OperationAESENCLASTSTATE ← SRC1;RoundKey ← SRC2;STATE ← ShiftRows( STATE );STATE ← SubBytes( STATE );DEST[127:0] ← STATE XOR RoundKey;DEST[255:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentAESENCLAST __m128i _mm_aesenclast (__m128i, __m128i)SIMD Floating-Point ExceptionsNoneAESENCLAST—Perform Last Round of an AES Encryption FlowVol. 2A 3-63INSTRUCTION SET REFERENCE, A-MProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.3-64 Vol.
2AAESENCLAST—Perform Last Round of an AES Encryption FlowINSTRUCTION SET REFERENCE, A-M#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.AESENCLAST—Perform Last Round of an AES Encryption FlowVol. 2A 3-65INSTRUCTION SET REFERENCE, A-MAESIMC—Perform the AES InvMixColumn TransformationOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 38 DB /rAESIMC xmm1,xmm2/m128AValidValidPerform the InvMixColumntransformation on a 128-bitround key fromxmm2/m128 and store theresult in xmm1.Instruction Operand EncodingOp/EnOperand 1Operand2Operand3Operand4AModRM:reg (w)ModRM:r/m (r)NANADescriptionPerform the InvMixColumns transformation on the source operand and store theresult in the destination operand.
The destination operand is an XMM register. Thesource operand can be an XMM register or a 128-bit memory location.Note the AESIMC instruction should be applied to the expanded AES round keys(except for the first and last round key) in order to prepare them for decryption usingthe “Equivalent Inverse Cipher” (defined in FIPS 197).OperationDEST[127:0] ← InvMixColumns( SRC );DEST[255:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentAESIMC __m128i _mm_aesimc (__m128i)SIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.3-66 Vol. 2AAESIMC—Perform the AES InvMixColumn TransformationINSTRUCTION SET REFERENCE, A-M#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.AESIMC—Perform the AES InvMixColumn TransformationVol.
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