Volume 2A Instruction Set Reference A-M (794101), страница 24
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2A 3-47INSTRUCTION SET REFERENCE, A-M#NMIf TS bit in CR0 is 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1.#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1.#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.3-48 Vol.
2AADDSUBPD—Packed Double-FP Add/SubtractINSTRUCTION SET REFERENCE, A-M#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.ADDSUBPD—Packed Double-FP Add/SubtractVol. 2A 3-49INSTRUCTION SET REFERENCE, A-MADDSUBPS—Packed Single-FP Add/SubtractOpcodeInstructionOp/EnF2 0F D0 /rADDSUBPS xmm1, Axmm2/m12864-bitModeCompat/ DescriptionLeg ModeValidValidAdd/subtract singleprecision floating-pointvalues from xmm2/m128 toxmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionAdds odd-numbered single-precision floating-point values of the source operand(second operand) with the corresponding single-precision floating-point values fromthe destination operand (first operand); stores the result in the odd-numberedvalues of the destination operand.Subtracts the even-numbered single-precision floating-point values in the sourceoperand from the corresponding single-precision floating values in the destinationoperand; stores the result into the even-numbered values of the destinationoperand.The source operand can be a 128-bit memory location or an XMM register.
The destination operand is an XMM register. See Figure 3-4.$''68%36[PP[PPP>@>@>@>@[PP>@[PPP>@[PP>@[PPP>@[PP>@[PPP>@[PP>@[PPP>@>@>@>@>@[PPP5(68/7[PP20Figure 3-4. ADDSUBPS—Packed Single-FP Add/Subtract3-50 Vol. 2AADDSUBPS—Packed Single-FP Add/SubtractINSTRUCTION SET REFERENCE, A-MIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).Operationxmm1[31:0] = xmm1[31:0] - xmm2/m128[31:0];xmm1[63:32] = xmm1[63:32] + xmm2/m128[63:32];xmm1[95:64] = xmm1[95:64] - xmm2/m128[95:64];xmm1[127:96] = xmm1[127:96] + xmm2/m128[127:96];Intel C/C++ Compiler Intrinsic EquivalentADDSUBPS__m128 _mm_addsub_ps(__m128 a, __m128 b)ExceptionsWhen the source operand is a memory operand, the operand must be aligned on a16-byte boundary or a general-protection exception (#GP) will be generated.SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1.#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.ADDSUBPS—Packed Single-FP Add/SubtractVol.
2A 3-51INSTRUCTION SET REFERENCE, A-MIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1.#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Virtual 8086 Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1.#UDIf CR0.EM[bit 2] = 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)#GP(0)If a memory address referencing the SS segment is in a noncanonical form.If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.3-52 Vol.
2AADDSUBPS—Packed Single-FP Add/SubtractINSTRUCTION SET REFERENCE, A-M#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.ADDSUBPS—Packed Single-FP Add/SubtractVol. 2A 3-53INSTRUCTION SET REFERENCE, A-MAESDEC—Perform One Round of an AES Decryption FlowOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 38 DE /rAESDEC xmm1,xmm2/m128AValidValidPerform one round of anAES decryption flow, usingthe Equivalent InverseCipher, operating on a 128bit data (state) from xmm1with a 128-bit round keyfrom xmm2/m128.Instruction Operand EncodingOp/EnOperand 1Operand2Operand3Operand4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionThis instruction performs a single round of the AES decryption flow using the Equivalent Inverse Cipher, with the round key from the second source operand, operatingon a 128-bit data (state) from the first source operand, and store the result in thedestination operand.Use the AESDEC instruction for all but the last decryption round.
For the last decryption round, use the AESDECCLAST instruction.The first source operand and the destination operand are the same and must be anXMM register. The second source operand can be an XMM register or a 128-bitmemory location.OperationAESDECSTATE ← SRC1;RoundKey ← SRC2;STATE ← InvShiftRows( STATE );STATE ← InvSubBytes( STATE );STATE ← InvMixColumns( STATE );DEST[127:0] ← STATE XOR RoundKey;DEST[255:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentAESDEC __m128i _mm_aesdec (__m128i, __m128i)3-54 Vol. 2AAESDEC—Perform One Round of an AES Decryption FlowINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.AESDEC—Perform One Round of an AES Decryption FlowVol.
2A 3-55INSTRUCTION SET REFERENCE, A-MIf memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.3-56 Vol. 2AAESDEC—Perform One Round of an AES Decryption FlowINSTRUCTION SET REFERENCE, A-MAESDECLAST—Perform Last Round of an AES Decryption FlowOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 38 DF /rAESDECLASTxmm1,xmm2/m128AValidValidPerform the last round of anAES decryption flow, usingthe Equivalent InverseCipher, operating on a 128bit data (state) from xmm1with a 128-bit round keyfrom xmm2/m128.Instruction Operand EncodingOp/EnOperand 1Operand2Operand3Operand4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionThis instruction performs the last round of the AES decryption flow using the Equivalent Inverse Cipher, with the round key from the second source operand, operatingon a 128-bit data (state) from the first source operand, and store the result in thedestination operand.The first source operand and the destination operand are the same and must be anXMM register.
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