Volume 2A Instruction Set Reference A-M (794101), страница 21
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The AAD instruction is only usefulwhen it precedes a DIV instruction that divides (binary division) the adjusted value inthe AX register by an unpacked BCD value.The AAD instruction sets the value in the AL register to (AL + (10 * AH)), and thenclears the AH register to 00H. The value in the AX register is then equal to the binaryequivalent of the original unpacked two-digit (base 10) number in registers AHand AL.The generalized version of this instruction allows adjustment of two unpacked digitsof any number base (see the “Operation” section below), by setting the imm8 byte tothe selected number base (for example, 08H for octal, 0AH for decimal, or 0CH forbase 12 numbers). The AAD mnemonic is interpreted by all assemblers to meanadjust ASCII (base 10) values.
To adjust values in another number base, the instruction must be hand coded in machine code (D5 imm8).This instruction executes as described in compatibility mode and legacy mode. It isnot valid in 64-bit mode.OperationIF 64-Bit ModeTHEN#UD;ELSEtempAL ← AL;tempAH ← AH;AL ← (tempAL + (tempAH ∗ imm8)) AND FFH;(* imm8 is set to 0AH for the AAD mnemonic.*)AAD—ASCII Adjust AX Before DivisionVol. 2A 3-21INSTRUCTION SET REFERENCE, A-MAH ← 0;FI;The immediate value (imm8) is taken from the second byte of the instruction.Flags AffectedThe SF, ZF, and PF flags are set according to the resulting binary value in the ALregister; the OF, AF, and CF flags are undefined.Protected Mode Exceptions#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as protected mode.Virtual-8086 Mode ExceptionsSame exceptions as protected mode.Compatibility Mode ExceptionsSame exceptions as protected mode.64-Bit Mode Exceptions#UD3-22 Vol.
2AIf in 64-bit mode.AAD—ASCII Adjust AX Before DivisionINSTRUCTION SET REFERENCE, A-MAAM—ASCII Adjust AX After MultiplyOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg ModeD4 0AAAMAInvalidValidASCII adjust AX aftermultiply.D4 ib(No mnemonic)AInvalidValidAdjust AX after multiply tonumber base imm8.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionAdjusts the result of the multiplication of two unpacked BCD values to create a pairof unpacked (base 10) BCD values.
The AX register is the implied source and destination operand for this instruction. The AAM instruction is only useful when it followsan MUL instruction that multiplies (binary multiplication) two unpacked BCD valuesand stores a word result in the AX register. The AAM instruction then adjusts thecontents of the AX register to contain the correct 2-digit unpacked (base 10) BCDresult.The generalized version of this instruction allows adjustment of the contents of theAX to create two unpacked digits of any number base (see the “Operation” sectionbelow). Here, the imm8 byte is set to the selected number base (for example, 08Hfor octal, 0AH for decimal, or 0CH for base 12 numbers).
The AAM mnemonic is interpreted by all assemblers to mean adjust to ASCII (base 10) values. To adjust tovalues in another number base, the instruction must be hand coded in machine code(D4 imm8).This instruction executes as described in compatibility mode and legacy mode. It isnot valid in 64-bit mode.OperationIF 64-Bit ModeTHEN#UD;ELSEtempAL ← AL;AH ← tempAL / imm8; (* imm8 is set to 0AH for the AAM mnemonic *)AL ← tempAL MOD imm8;FI;The immediate value (imm8) is taken from the second byte of the instruction.AAM—ASCII Adjust AX After MultiplyVol. 2A 3-23INSTRUCTION SET REFERENCE, A-MFlags AffectedThe SF, ZF, and PF flags are set according to the resulting binary value in the ALregister.
The OF, AF, and CF flags are undefined.Protected Mode Exceptions#DEIf an immediate value of 0 is used.#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as protected mode.Virtual-8086 Mode ExceptionsSame exceptions as protected mode.Compatibility Mode ExceptionsSame exceptions as protected mode.64-Bit Mode Exceptions#UD3-24 Vol. 2AIf in 64-bit mode.AAM—ASCII Adjust AX After MultiplyINSTRUCTION SET REFERENCE, A-MAAS—ASCII Adjust AL After SubtractionOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode3FAASAInvalidValidASCII adjust AL aftersubtraction.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionAdjusts the result of the subtraction of two unpacked BCD values to create aunpacked BCD result.
The AL register is the implied source and destination operandfor this instruction. The AAS instruction is only useful when it follows a SUB instruction that subtracts (binary subtraction) one unpacked BCD value from another andstores a byte result in the AL register. The AAA instruction then adjusts the contentsof the AL register to contain the correct 1-digit unpacked BCD result.If the subtraction produced a decimal carry, the AH register decrements by 1, and theCF and AF flags are set. If no decimal carry occurred, the CF and AF flags are cleared,and the AH register is unchanged. In either case, the AL register is left with its topfour bits set to 0.This instruction executes as described in compatibility mode and legacy mode.
It isnot valid in 64-bit mode.OperationIF 64-bit modeTHEN#UD;ELSEIF ((AL AND 0FH) > 9) or (AF = 1)THENAL ← AL – 6;AH ← AH – 1;AF ← 1;CF ← 1;AL ← AL AND 0FH;ELSECF ← 0;AF ← 0;AL ← AL AND 0FH;AAS—ASCII Adjust AL After SubtractionVol. 2A 3-25INSTRUCTION SET REFERENCE, A-MFI;FI;Flags AffectedThe AF and CF flags are set to 1 if there is a decimal borrow; otherwise, they arecleared to 0. The OF, SF, ZF, and PF flags are undefined.Protected Mode Exceptions#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as protected mode.Virtual-8086 Mode ExceptionsSame exceptions as protected mode.Compatibility Mode ExceptionsSame exceptions as protected mode.64-Bit Mode Exceptions#UD3-26 Vol. 2AIf in 64-bit mode.AAS—ASCII Adjust AL After SubtractionINSTRUCTION SET REFERENCE, A-MADC—Add with CarryOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode14 ibADC AL, imm8CValidValidAdd with carry imm8 to AL.15 iwADC AX, imm16CValidValidAdd with carry imm16 toAX.15 idADC EAX, imm32CValidValidAdd with carry imm32 toEAX.REX.W + 15 idADC RAX, imm32CValidN.E.Add with carry imm32 signextended to 64-bits to RAX.80 /2 ibADC r/m8, imm8BValidValidAdd with carry imm8 tor/m8.REX + 80 /2 ibADC r/m8*, imm8BValidN.E.Add with carry imm8 tor/m8.81 /2 iwADC r/m16,imm16BValidValidAdd with carry imm16 tor/m16.81 /2 idADC r/m32,imm32BValidValidAdd with CF imm32 tor/m32.REX.W + 81 /2idADC r/m64,imm32BValidN.E.Add with CF imm32 signextended to 64-bits tor/m64.83 /2 ibADC r/m16, imm8BValidValidAdd with CF sign-extendedimm8 to r/m16.83 /2 ibADC r/m32, imm8BValidValidAdd with CF sign-extendedimm8 into r/m32.REX.W + 83 /2ibADC r/m64, imm8BValidN.E.Add with CF sign-extendedimm8 into r/m64.10 /rADC r/m8, r8AValidValidAdd with carry byte registerto r/m8.REX + 10 /rADC r/m8*, r8*AValidN.E.Add with carry byte registerto r/m64.11 /rADC r/m16, r16AValidValidAdd with carry r16 tor/m16.11 /rADC r/m32, r32AValidValidAdd with CF r32 to r/m32.REX.W + 11 /rADC r/m64, r64AValidN.E.Add with CF r64 to r/m64.12 /rADC r8, r/m8AValidValidAdd with carry r/m8 to byteregister.REX + 12 /rADC r8*, r/m8*AValidN.E.Add with carry r/m64 tobyte register.ADC—Add with CarryVol.
2A 3-27INSTRUCTION SET REFERENCE, A-MOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode13 /rADC r16, r/m16AValidValidAdd with carry r/m16 tor16.13 /rADC r32, r/m32AValidValidAdd with CF r/m32 to r32.REX.W + 13 /rADC r64, r/m64AValidN.E.Add with CF r/m64 to r64.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)ModRM:reg (r)NANABModRM:r/m (r, w)imm8NANACAL/AX/EAX/RAXimm8NANADescriptionAdds the destination operand (first operand), the source operand (second operand),and the carry (CF) flag and stores the result in the destination operand.
The destination operand can be a register or a memory location; the source operand can be animmediate, a register, or a memory location. (However, two memory operandscannot be used in one instruction.) The state of the CF flag represents a carry from aprevious addition. When an immediate value is used as an operand, it is signextended to the length of the destination operand format.The ADC instruction does not distinguish between signed or unsigned operands.Instead, the processor evaluates the result for both data types and sets the OF andCF flags to indicate a carry in the signed or unsigned result, respectively. The SF flagindicates the sign of the signed result.The ADC instruction is usually executed as part of a multibyte or multiword additionin which an ADD instruction is followed by an ADC instruction.This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, the instruction’s default operation size is 32 bits.
Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationDEST ← DEST + SRC + CF;3-28 Vol. 2AADC—Add with CarryINSTRUCTION SET REFERENCE, A-MFlags AffectedThe OF, SF, ZF, AF, CF, and PF flags are set according to the result.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.ADC—Add with CarryVol.
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