Volume 2A Instruction Set Reference A-M (794101), страница 17
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The following is a list of the symbols used to represent operands in the instruction statements:•rel8 — A relative address in the range from 128 bytes before the end of theinstruction to 127 bytes after the end of the instruction.•rel16, rel32, rel64 — A relative address within the same code segment as theinstruction assembled. The rel16 symbol applies to instructions with an operandsize attribute of 16 bits; the rel32 symbol applies to instructions with anoperand-size attribute of 32 bits; the rel64 symbol applies to instructions with anoperand-size attribute of 64 bits.Vol. 2A 3-3INSTRUCTION SET REFERENCE, A-M•ptr16:16, ptr16:32 and ptr16:64 — A far pointer, typically to a code segmentdifferent from that of the instruction.
The notation 16:16 indicates that the valueof the pointer has two parts. The value to the left of the colon is a 16-bit selectoror value destined for the code segment register. The value to the rightcorresponds to the offset within the destination segment. The ptr16:16 symbol isused when the instruction's operand-size attribute is 16 bits; the ptr16:32symbol is used when the operand-size attribute is 32 bits; the ptr16:64 symbol isused when the operand-size attribute is 64 bits.•r8 — One of the byte general-purpose registers: AL, CL, DL, BL, AH, CH, DH, BH,BPL, SPL, DIL and SIL; or one of the byte registers (R8L - R15L) available whenusing REX.R and 64-bit mode.•r16 — One of the word general-purpose registers: AX, CX, DX, BX, SP, BP, SI, DI;or one of the word registers (R8-R15) available when using REX.R and 64-bitmode.•r32 — One of the doubleword general-purpose registers: EAX, ECX, EDX, EBX,ESP, EBP, ESI, EDI; or one of the doubleword registers (R8D - R15D) availablewhen using REX.R in 64-bit mode.•r64 — One of the quadword general-purpose registers: RAX, RBX, RCX, RDX,RDI, RSI, RBP, RSP, R8–R15.
These are available when using REX.R and 64-bitmode.•imm8 — An immediate byte value. The imm8 symbol is a signed numberbetween –128 and +127 inclusive. For instructions in which imm8 is combinedwith a word or doubleword operand, the immediate value is sign-extended toform a word or doubleword.
The upper byte of the word is filled with the topmostbit of the immediate value.•imm16 — An immediate word value used for instructions whose operand-sizeattribute is 16 bits. This is a number between –32,768 and +32,767 inclusive.•imm32 — An immediate doubleword value used for instructions whoseoperand-size attribute is 32 bits. It allows the use of a number between+2,147,483,647 and –2,147,483,648 inclusive.•imm64 — An immediate quadword value used for instructions whoseoperand-size attribute is 64 bits. The value allows the use of a numberbetween +9,223,372,036,854,775,807 and –9,223,372,036,854,775,808inclusive.•r/m8 — A byte operand that is either the contents of a byte general-purposeregister (AL, CL, DL, BL, AH, CH, DH, BH, BPL, SPL, DIL and SIL) or a byte frommemory.
Byte registers R8L - R15L are available using REX.R in 64-bit mode.•r/m16 — A word general-purpose register or memory operand used for instructions whose operand-size attribute is 16 bits. The word general-purpose registersare: AX, CX, DX, BX, SP, BP, SI, DI. The contents of memory are found at theaddress provided by the effective address computation. Word registers R8W R15W are available using REX.R in 64-bit mode.3-4 Vol. 2AINSTRUCTION SET REFERENCE, A-M•r/m32 — A doubleword general-purpose register or memory operand used forinstructions whose operand-size attribute is 32 bits.
The doubleword generalpurpose registers are: EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI. The contents ofmemory are found at the address provided by the effective address computation.Doubleword registers R8D - R15D are available when using REX.R in 64-bitmode.•r/m64 — A quadword general-purpose register or memory operand used forinstructions whose operand-size attribute is 64 bits when using REX.W.Quadword general-purpose registers are: RAX, RBX, RCX, RDX, RDI, RSI, RBP,RSP, R8–R15; these are available only in 64-bit mode.
The contents of memoryare found at the address provided by the effective address computation.••m — A 16-, 32- or 64-bit operand in memory.•m16 — A word operand in memory, usually expressed as a variable or arrayname, but pointed to by the DS:(E)SI or ES:(E)DI registers. This nomenclature isused only with the string instructions.•m32 — A doubleword operand in memory, usually expressed as a variable orarray name, but pointed to by the DS:(E)SI or ES:(E)DI registers.
This nomenclature is used only with the string instructions.•••m64 — A memory quadword operand in memory.•m16&32, m16&16, m32&32, m16&64 — A memory operand consisting ofdata item pairs whose sizes are indicated on the left and the right side of theampersand. All memory addressing modes are allowed. The m16&16 andm32&32 operands are used by the BOUND instruction to provide an operandcontaining an upper and lower bounds for array indices. The m16&32 operand isused by LIDT and LGDT to provide a word with which to load the limit field, and adoubleword with which to load the base field of the corresponding GDTR andIDTR registers.
The m16&64 operand is used by LIDT and LGDT in 64-bit mode toprovide a word with which to load the limit field, and a quadword with which toload the base field of the corresponding GDTR and IDTR registers.•moffs8, moffs16, moffs32, moffs64 — A simple memory variable (memoryoffset) of type byte, word, or doubleword used by some variants of the MOVinstruction.
The actual address is given by a simple offset relative to the segmentbase. No ModR/M byte is used in the instruction. The number shown with moffsindicates its size, which is determined by the address-size attribute of theinstruction.m8 — A byte operand in memory, usually expressed as a variable or array name,but pointed to by the DS:(E)SI or ES:(E)DI registers. In 64-bit mode, it is pointedto by the RSI or RDI registers.m128 — A memory double quadword operand in memory.m16:16, m16:32 & m16:64 — A memory operand containing a far pointercomposed of two numbers.
The number to the left of the colon corresponds to thepointer's segment selector. The number to the right corresponds to its offset.Vol. 2A 3-5INSTRUCTION SET REFERENCE, A-M•Sreg — A segment register. The segment register bit assignments are ES = 0,CS = 1, SS = 2, DS = 3, FS = 4, and GS = 5.•m32fp, m64fp, m80fp — A single-precision, double-precision, and doubleextended-precision (respectively) floating-point operand in memory. Thesesymbols designate floating-point values that are used as operands for x87 FPUfloating-point instructions.•m16int, m32int, m64int — A word, doubleword, and quadword integer(respectively) operand in memory.
These symbols designate integers that areused as operands for x87 FPU integer instructions.••••ST or ST(0) — The top element of the FPU register stack.•mm/m64 — An MMX register or a 64-bit memory operand. The 64-bit MMXregisters are: MM0 through MM7. The contents of memory are found at theaddress provided by the effective address computation.•xmm — An XMM register. The 128-bit XMM registers are: XMM0 through XMM7;XMM8 through XMM15 are available using REX.R in 64-bit mode.•xmm/m32— An XMM register or a 32-bit memory operand. The 128-bit XMMregisters are XMM0 through XMM7; XMM8 through XMM15 are available usingREX.R in 64-bit mode. The contents of memory are found at the address providedby the effective address computation.•xmm/m64 — An XMM register or a 64-bit memory operand. The 128-bit SIMDfloating-point registers are XMM0 through XMM7; XMM8 through XMM15 areavailable using REX.R in 64-bit mode.
The contents of memory are found at theaddress provided by the effective address computation.•xmm/m128 — An XMM register or a 128-bit memory operand. The 128-bit XMMregisters are XMM0 through XMM7; XMM8 through XMM15 are available usingREX.R in 64-bit mode. The contents of memory are found at the address providedby the effective address computation.•<XMM0>: indicates implied use of the XMM0 register.ST(i) — The ith element from the top of the FPU register stack (i ← 0 through 7).mm — An MMX register. The 64-bit MMX registers are: MM0 through MM7.mm/m32 — The low order 32 bits of an MMX register or a 32-bit memoryoperand.
The 64-bit MMX registers are: MM0 through MM7. The contents ofmemory are found at the address provided by the effective address computation.When there is ambiguity, xmm1 indicates the first source operand using an XMMregister and xmm2 the second source operand using an XMM register.Some instructions use the XMM0 register as the third source operand, indicatedby <XMM0>.
The use of the third XMM register operand is implicit in the instruction encoding and does not affect the ModR/M encoding.3-6 Vol. 2AINSTRUCTION SET REFERENCE, A-M3.1.1.3Operand Encoding Column in the Instruction Summary TableThe “operand encoding” column is abbreviated as Op/En in the Instruction Summarytable heading. Instruction operand encoding information is provided for eachassembly instruction syntax using a letter to cross reference to a row entry in theoperand encoding definition table that follows the instruction summary table. Thedefinition table is organized according to the order of operand in Intel assemblysyntax. The encoding method for each operand in the instruction byte stream isexpressed via modR/M:reg, modR/M:r/m, imm8/16/32/64, etc.
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