Volume 2A Instruction Set Reference A-M (794101), страница 13
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Bit positions are numberedfrom right to left. The numerical value of a set bit is equal to two raised to the powerof the bit position. IA-32 processors are “little endian” machines; this means thebytes of a word are numbered starting from the least significant byte. Figure 1-1illustrates these conventions.1-4 Vol. 2AABOUT THIS MANUALHighestAddress 3124 23Byte 3Data Structure8 716 15Byte 2Byte 10Byte 0Bit offset2824201612840LowestAddressByte OffsetFigure 1-1. Bit and Byte Order1.3.2Reserved Bits and Software CompatibilityIn many register and memory layout descriptions, certain bits are marked asreserved.
When bits are marked as reserved, it is essential for compatibility withfuture processors that software treat these bits as having a future, though unknown,effect. The behavior of reserved bits should be regarded as not only undefined, butunpredictable. Software should follow these guidelines in dealing with reserved bits:•Do not depend on the states of any reserved bits when testing the values ofregisters which contain such bits.
Mask out the reserved bits before testing.•Do not depend on the states of any reserved bits when storing to memory or to aregister.••Do not depend on the ability to retain information written into any reserved bits.When loading a register, always load the reserved bits with the values indicatedin the documentation, if any, or reload them with values previously read from thesame register.NOTEAvoid any software dependence upon the state of reserved bits inIA-32 registers. Depending upon the values of reserved register bitswill make software dependent upon the unspecified manner in whichthe processor handles these bits.
Programs that depend uponreserved values risk incompatibility with future processors.Vol. 2A 1-5ABOUT THIS MANUAL1.3.3Instruction OperandsWhen instructions are represented symbolically, a subset of the IA-32 assemblylanguage is used. In this subset, an instruction has the following format:label: mnemonic argument1, argument2, argument3where:••A label is an identifier which is followed by a colon.•The operands argument1, argument2, and argument3 are optional.
There maybe from zero to three operands, depending on the opcode. When present, theytake the form of either literals or identifiers for data items. Operand identifiersare either reserved names of registers or are assumed to be assigned to dataitems declared in another part of the program (which may not be shown in theexample).A mnemonic is a reserved name for a class of instruction opcodes which havethe same function.When two operands are present in an arithmetic or logical instruction, the rightoperand is the source and the left operand is the destination.For example:LOADREG: MOV EAX, SUBTOTALIn this example, LOADREG is a label, MOV is the mnemonic identifier of an opcode,EAX is the destination operand, and SUBTOTAL is the source operand. Someassembly languages put the source and destination in reverse order.1.3.4Hexadecimal and Binary NumbersBase 16 (hexadecimal) numbers are represented by a string of hexadecimal digitsfollowed by the character H (for example, F82EH).
A hexadecimal digit is a characterfrom the following set: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, and F.Base 2 (binary) numbers are represented by a string of 1s and 0s, sometimesfollowed by the character B (for example, 1010B). The “B” designation is only used insituations where confusion as to the type of number might arise.1.3.5Segmented AddressingThe processor uses byte addressing.
This means memory is organized and accessedas a sequence of bytes. Whether one or more bytes are being accessed, a byteaddress is used to locate the byte or bytes in memory. The range of memory that canbe addressed is called an address space.The processor also supports segmented addressing. This is a form of addressingwhere a program may have many independent address spaces, called segments.1-6 Vol. 2AABOUT THIS MANUALFor example, a program can keep its code (instructions) and stack in separatesegments. Code addresses would always refer to the code space, and stackaddresses would always refer to the stack space. The following notation is used tospecify a byte address within a segment:Segment-register:Byte-addressFor example, the following segment address identifies the byte at address FF79H inthe segment pointed by the DS register:DS:FF79HThe following segment address identifies an instruction address in the code segment.The CS register points to the code segment and the EIP register contains the addressof the instruction.CS:EIP1.3.6ExceptionsAn exception is an event that typically occurs when an instruction causes an error.For example, an attempt to divide by zero generates an exception.
However, someexceptions, such as breakpoints, occur under other conditions. Some types of exceptions may provide error codes. An error code reports additional information about theerror. An example of the notation used to show an exception and error code is shownbelow:#PF(fault code)This example refers to a page-fault exception under conditions where an error codenaming a type of fault is reported.
Under some conditions, exceptions which produceerror codes may not be able to report an accurate code. In this case, the error codeis zero, as shown below for a general-protection exception:#GP(0)1.3.7A New Syntax for CPUID, CR, and MSR ValuesObtain feature flags, status, and system information by using the CPUID instruction,by checking control register bits, and by reading model-specific registers. We aremoving toward a new syntax to represent this information.
See Figure 1-2.Vol. 2A 1-7ABOUT THIS MANUAL&38,',QSXWDQG2XWSXW&38,'+(&;66(>ELW@ 6RPHLQSXWVUHTXLUHYDOXHVLQ($;DQG(&;7KLVLVUHSUHVHQWHGDV&38,'($; Q(&; Q,IRQO\RQHYDOXHLVSUHVHQW($;LVLPSOLHG2XWSXWUHJLVWHUDQGIHDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW&RQWURO5HJLVWHU9DOXHV&526);65>ELW@ ([DPSOH&5QDPH)HDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW0RGHO6SHFLILF5HJLVWHU9DOXHV,$B0,6&B(1$%/(6(1$%/()23&2'(>ELW@ ([DPSOH065QDPH)HDWXUHIODJRUILHOGQDPHZLWKELWSRVLWLRQV9DOXHRUUDQJHRIRXWSXW20Figure 1-2.
Syntax for CPUID, CR, and MSR Data Presentation1.4RELATED LITERATURELiterature related to Intel 64 and IA-32 processors is listed on-line at:http://developer.intel.com/products/processor/manuals/index.htmSome of the documents listed at this web site can be viewed on-line; others can beordered. The literature available is listed by Intel processor and then by the following1-8 Vol. 2AABOUT THIS MANUALliterature types: applications notes, data sheets, manuals, papers, and specificationupdates.See also:•••The data sheet for a particular Intel 64 or IA-32 processor•Intel® Fortran Compiler documentation and online helphttp://www.intel.com/cd/software/products/asmo-na/eng/index.htm•Intel® VTune™ Performance Analyzer documentation and online helphttp://www.intel.com/cd/software/products/asmo-na/eng/index.htm•Intel® 64 and IA-32 Architectures Software Developer’s Manual (in five volumes)http://developer.intel.com/products/processor/manuals/index.htm•Intel® 64 and IA-32 Architectures Optimization Reference Manualhttp://developer.intel.com/products/processor/manuals/index.htm•Intel® Processor Identification with the CPUID Instruction, AP-485http://www.intel.com/support/processors/sb/cs-009861.htm•Intel 64 Architecture x2APIC Specification:The specification update for a particular Intel 64 or IA-32 processorIntel® C++ Compiler documentation and online helphttp://www.intel.com/cd/software/products/asmo-na/eng/index.htmhttp://developer.intel.com/products/processor/manuals/index.htm•Intel 64 Architecture Processor Topology Enumeration:http://softwarecommunity.intel.com/articles/eng/3887.htm•Intel® Trusted Execution Technology Measured Launched EnvironmentProgramming Guide, http://www.intel.com/technology/security/index.htm•Intel® SSE4 Programming Reference,http://developer.intel.com/products/processor/manuals/index.htm•Developing Multi-threaded Applications: A Platform Consistent Approach•Using Spin-Loops on Intel Pentium 4 Processor and Intel Xeon Processor MPhttp://www3.intel.com/cd/ids/developer/asmona/eng/dc/threading/knowledgebase/19083.htmhttp://cachewww.intel.com/cd/00/00/05/15/51534_developing_multithreaded_applications.pdfMore relevant links are:•Software network link:http://softwarecommunity.intel.com/isn/home/•Developer centers:http://www.intel.com/cd/ids/developer/asmo-na/eng/dc/index.htm•Processor support general link:http://www.intel.com/support/processors/Vol.
2A 1-9ABOUT THIS MANUAL•Software products and packages:http://www.intel.com/cd/software/products/asmo-na/eng/index.htm•Intel 64 and IA-32 processor manuals (printed or PDF downloads):http://developer.intel.com/products/processor/manuals/index.htm•Intel® Multi-Core Technology:http://developer.intel.com/multi-core/index.htm•Intel® Hyper-Threading Technology (Intel® HT Technology):http://developer.intel.com/technology/hyperthread/1-10 Vol. 2ACHAPTER 2INSTRUCTION FORMATThis chapter describes the instruction format for all Intel 64 and IA-32 processors.The instruction format for protected mode, real-address mode and virtual-8086mode is described in Section 2.1.
Increments provided for IA-32e mode and its submodes are described in Section 2.2.2.1INSTRUCTION FORMAT FOR PROTECTED MODE,REAL-ADDRESS MODE, AND VIRTUAL-8086 MODEThe Intel 64 and IA-32 architectures instruction encodings are subsets of the formatshown in Figure 2-1. Instructions consist of optional instruction prefixes (in anyorder), primary opcode bytes (up to three bytes), an addressing-form specifier (ifrequired) consisting of the ModR/M byte and sometimes the SIB (Scale-Index-Base)byte, a displacement (if required), and an immediate data field (if required).InstructionPrefixesUp to fourprefixes of1 byte each(optional)OpcodeModR/MSIB1-, 2-, or 3-byte 1 byteopcode(if required)76 5ModReg/Opcode3 20R/MDisplacement1 byte(if required)7Addressdisplacementof 1, 2, or 4bytes or none3 26 5ScaleIndexImmediateImmediatedata of1, 2, or 4bytes or none0BaseFigure 2-1.
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