Volume 2A Instruction Set Reference A-M (794101), страница 12
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. . . . . . . . . . . . . . . . . . . . . . . . . . . . B-93Encodings of SSE4.1 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-97Encodings of SSE4.2 instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-105CONTENTSPAGETable B-36.Table B-37.Table B-38.Table B-39.Table C-1.Table C-2.General Floating-Point Instruction Formats . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-107Floating-Point Instruction Formats and Encodings . . . . . . . . . . . . . . . . . . . . . . . . . . . B-108Encodings for VMX Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-113Encodings for SMX Instructions . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B-115Simple Intrinsics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . C-3Composite Intrinsics . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .C-16Vol. 2A xxiCONTENTSPAGExxii Vol. 2ACHAPTER 1ABOUT THIS MANUALThe Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes2A & 2B: Instruction Set Reference (order numbers 253666 and 253667) are part ofa set that describes the architecture and programming environment of all Intel 64and IA-32 architecture processors. Other volumes in this set are:•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1:Basic Architecture (Order Number 253665).•The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes3A & 3B: System Programming Guide (order numbers 253668 and 253669).The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1,describes the basic architecture and programming environment of Intel 64 and IA-32processors.
The Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volumes 2A & 2B, describe the instruction set of the processor and the opcode structure. These volumes apply to application programmers and to programmers whowrite operating systems or executives. The Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volumes 3A & 3B, describe the operating-system supportenvironment of Intel 64 and IA-32 processors. These volumes target operatingsystem and BIOS designers.
In addition, the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 3B, addresses the programming environment forclasses of software that host operating systems.1.1IA-32 PROCESSORS COVERED IN THIS MANUALThis manual set includes information pertaining primarily to the most recent Intel 64and IA-32 processors, which include:•••••••••••Pentium® processorsP6 family processorsPentium® 4 processorsPentium® M processorsIntel® Xeon® processorsPentium® D processorsPentium® processor Extreme Editions64-bit Intel® Xeon® processorsIntel® Core™ Duo processorIntel® Core™ Solo processorDual-Core Intel® Xeon® processor LVVol.
2A 1-1ABOUT THIS MANUAL•••••••••••••••••Intel® Core™2 Duo processorIntel® Core™2 Quad processor Q6000 seriesIntel® Xeon® processor 3000, 3200 seriesIntel® Xeon® processor 5000 seriesIntel® Xeon® processor 5100, 5300 seriesIntel® Core™2 Extreme processor X7000 and X6800 seriesIntel® Core™2 Extreme QX6000 seriesIntel® Xeon® processor 7100 seriesIntel® Pentium® Dual-Core processorIntel® Xeon® processor 7200, 7300 seriesIntel® Xeon® processor 5200, 5400, 7400 seriesIntel® CoreTM2 Extreme processor QX9000 and X9000 seriesIntel® CoreTM2 Quad processor Q9000 seriesIntel® CoreTM2 Duo processor E8000, T9000 seriesIntel® AtomTM processor familyIntel® CoreTM i7 processorIntel® CoreTM i5 processorP6 family processors are IA-32 processors based on the P6 family microarchitecture.This includes the Pentium® Pro, Pentium® II, Pentium® III, and Pentium® III Xeon®processors.The Pentium® 4, Pentium® D, and Pentium® processor Extreme Editions are basedon the Intel NetBurst® microarchitecture.
Most early Intel® Xeon® processors arebased on the Intel NetBurst® microarchitecture. Intel Xeon processor 5000, 7100series are based on the Intel NetBurst® microarchitecture.The Intel® Core™ Duo, Intel® Core™ Solo and dual-core Intel® Xeon® processor LVare based on an improved Pentium® M processor microarchitecture.The Intel® Xeon® processor 3000, 3200, 5100, 5300, 7200, and 7300 series, Intel®Pentium® dual-core, Intel® Core™2 Duo, Intel® Core™2 Quad, and Intel® Core™2Extreme processors are based on Intel® Core™ microarchitecture.The Intel® Xeon® processor 5200, 5400, 7400 series, Intel® CoreTM2 Quad processorQ9000 series, and Intel® CoreTM2 Extreme processors QX9000, X9000 series, Intel®CoreTM2 processor E8000 series are based on Enhanced Intel® CoreTM microarchitecture.The Intel® AtomTM processor family is based on the Intel® AtomTM microarchitectureand supports Intel 64 architecture.The Intel® CoreTM i7 processor and the Intel® CoreTM i5 processor are based on theIntel® microarchitecture codename Nehalem and support Intel 64 architecture.1-2 Vol.
2AABOUT THIS MANUALProcessors based on Intel® microarchitecture codename Westmere support Intel 64architecture.P6 family, Pentium® M, Intel® Core™ Solo, Intel® Core™ Duo processors, dual-coreIntel® Xeon® processor LV, and early generations of Pentium 4 and Intel Xeonprocessors support IA-32 architecture. The Intel® AtomTM processor Z5xx seriessupport IA-32 architecture.The Intel® Xeon® processor 3000, 3200, 5000, 5100, 5200, 5300, 5400, 7100,7200, 7300, 7400 series, Intel® Core™2 Duo, Intel® Core™2 Extreme, Intel®Core™2 Quad processors, Pentium® D processors, Pentium® Dual-Core processor,newer generations of Pentium 4 and Intel Xeon processor family support Intel® 64architecture.IA-32 architecture is the instruction set architecture and programming environmentfor Intel's 32-bit microprocessors.Intel® 64 architecture is the instruction set architecture and programming environment which is the superset of Intel’s 32-bit and 64-bit architectures.
It is compatiblewith the IA-32 architecture.1.2OVERVIEW OF VOLUME 2A AND 2B: INSTRUCTIONSET REFERENCEA description of Intel® 64 and IA-32 Architectures Software Developer’s Manual,Volumes 2A & 2B, content follows:Chapter 1 — About This Manual. Gives an overview of all five volumes of theIntel® 64 and IA-32 Architectures Software Developer’s Manual. It also describesthe notational conventions in these manuals and lists related Intel® manuals anddocumentation of interest to programmers and hardware designers.Chapter 2 — Instruction Format. Describes the machine-level instruction formatused for all IA-32 instructions and gives the allowable encodings of prefixes, theoperand-identifier byte (ModR/M byte), the addressing-mode specifier byte (SIBbyte), and the displacement and immediate bytes.Chapter 3 — Instruction Set Reference, A-M.
Describes Intel 64 and IA-32instructions in detail, including an algorithmic description of operations, the effect onflags, the effect of operand- and address-size attributes, and the exceptions thatmay be generated. The instructions are arranged in alphabetical order. Generalpurpose, x87 FPU, Intel MMX™ technology, SSE/SSE2/SSE3/SSSE3/SSE4 extensions, and system instructions are included.Chapter 4 — Instruction Set Reference, N-Z. Continues the description of Intel64 and IA-32 instructions started in Chapter 3. It provides the balance of the alphabetized list of instructions and starts Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 2B.Vol.
2A 1-3ABOUT THIS MANUALChapter 5 — VMX Instruction Reference. Describes the virtual-machine extensions (VMX). VMX is intended for a system executive to support virtualization ofprocessor hardware and a system software layer acting as a host to multiple guestsoftware environments.Chapter 6— Safer Mode Extensions Reference. Describes the safer mode extensions (SMX). SMX is intended for a system executive to support launching ameasured environment in a platform where the identity of the software controllingthe platform hardware can be measured for the purpose of making trust decisions.Appendix A — Opcode Map. Gives an opcode map for the IA-32 instruction set.Appendix B — Instruction Formats and Encodings.
Gives the binary encoding ofeach form of each IA-32 instruction.Appendix C — Intel® C/C++ Compiler Intrinsics and Functional Equivalents.Lists the Intel® C/C++ compiler intrinsics and their assembly code equivalents foreach of the IA-32 MMX and SSE/SSE2/SSE3 instructions.1.3NOTATIONAL CONVENTIONSThis manual uses specific notation for data-structure formats, for symbolic representation of instructions, and for hexadecimal and binary numbers. A review of thisnotation makes the manual easier to read.1.3.1Bit and Byte OrderIn illustrations of data structures in memory, smaller addresses appear toward thebottom of the figure; addresses increase toward the top.
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