Volume 2A Instruction Set Reference A-M (794101), страница 16
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Table 2-5 describes how each case behaves.2-12 Vol. 2AINSTRUCTION FORMATTable 2-5. Special Cases of REX EncodingsModR/M orSIBSub-fieldEncodingsModR/M Byte mod != 11CompatibilityMode OperationCompatibilityMode Implications Additional ImplicationsSIB byte present.SIB byte requiredfor ESP-basedaddressing.r/m ==b*100(ESP)ModR/M Byte mod == 0r/m ==b*101(EBP)REX prefix adds a fourthbit (b) which is notdecoded (don't care).SIB byte also required forR12-based addressing.Base register notused.EBP without adisplacement mustbe done usingREX prefix adds a fourthbit (b) which is notdecoded (don't care).mod = 01 withdisplacement of 0.Using RBP or R13 withoutdisplacement must bedone using mod = 01 witha displacement of 0.SIB Byteindex ==0100(ESP)Index register notused.ESP cannot be used REX prefix adds a fourthas an indexbit (b) which is decoded.register.There are no additionalimplications.
Theexpanded index fieldallows distinguishing RSPfrom R12, therefore R12can be used as an index.SIB Bytebase ==0101(EBP)Base register isunused ifmod = 0.Base registerdepends on modencoding.REX prefix adds a fourthbit (b) which is notdecoded.This requires explicitdisplacement to be usedwith EBP/RBP or R13.NOTES:* Don’t care about value of REX.B2.2.1.3DisplacementAddressing in 64-bit mode uses existing 32-bit ModR/M and SIB encodings.
TheModR/M and SIB displacement sizes do not change. They remain 8 bits or 32 bits andare sign-extended to 64 bits.2.2.1.4Direct Memory-Offset MOVsIn 64-bit mode, direct memory-offset forms of the MOV instruction are extended tospecify a 64-bit immediate absolute address. This address is called a moffset. Noprefix is needed to specify this 64-bit memory offset. For these MOV instructions, theVol. 2A 2-13INSTRUCTION FORMATsize of the memory offset follows the address-size default (64 bits in 64-bit mode).See Table 2-6.Table 2-6.
Direct Memory Offset Form of MOVOpcodeInstructionA0MOV AL, moffsetA1MOV EAX, moffsetA2MOV moffset, ALA3MOV moffset, EAX2.2.1.5ImmediatesIn 64-bit mode, the typical size of immediate operands remains 32 bits. When theoperand size is 64 bits, the processor sign-extends all immediates to 64 bits prior totheir use.Support for 64-bit immediate operands is accomplished by expanding the semanticsof the existing move (MOV reg, imm16/32) instructions.
These instructions (opcodesB8H – BFH) move 16-bits or 32-bits of immediate data (depending on the effectiveoperand size) into a GPR. When the effective operand size is 64 bits, these instructions can be used to load an immediate into a GPR. A REX prefix is needed to overridethe 32-bit default operand size to a 64-bit operand size.For example:48 B8 8877665544332211 MOV RAX,1122334455667788H2.2.1.6RIP-Relative AddressingA new addressing form, RIP-relative (relative instruction-pointer) addressing, isimplemented in 64-bit mode. An effective address is formed by adding displacementto the 64-bit RIP of the next instruction.In IA-32 architecture and compatibility mode, addressing relative to the instructionpointer is available only with control-transfer instructions.
In 64-bit mode, instructions that use ModR/M addressing can use RIP-relative addressing. Without RIP-relative addressing, all ModR/M instruction modes address memory relative to zero.RIP-relative addressing allows specific ModR/M modes to address memory relative tothe 64-bit RIP using a signed 32-bit displacement. This provides an offset range of±2GB from the RIP. Table 2-7 shows the ModR/M and SIB encodings for RIP-relativeaddressing. Redundant forms of 32-bit displacement-addressing exist in the currentModR/M and SIB encodings. There is one ModR/M encoding and there are several SIBencodings.
RIP-relative addressing is encoded using a redundant form.In 64-bit mode, the ModR/M Disp32 (32-bit displacement) encoding is re-defined tobe RIP+Disp32 rather than displacement-only. See Table 2-7.2-14 Vol. 2AINSTRUCTION FORMATTable 2-7. RIP-Relative AddressingModR/M and SIB Sub-fieldEncodingsCompatibilityMode Operation64-bit ModeOperationAdditional Implicationsin 64-bit modeModR/MBytemod == 00Disp32RIP + Disp32Must use SIB form withnormal (zero-based)displacement addressingSIB Bytebase == 101 (none)if mod = 00,Disp32Same aslegacyNoner/m == 101 (none)index == 100(none)scale = 0, 1, 2, 4The ModR/M encoding for RIP-relative addressing does not depend on using prefix.Specifically, the r/m bit field encoding of 101B (used to select RIP-relativeaddressing) is not affected by the REX prefix.
For example, selecting R13 (REX.B = 1,r/m = 101B) with mod = 00B still results in RIP-relative addressing. The 4-bit r/mfield of REX.B combined with ModR/M is not fully decoded. In order to address R13with no displacement, software must encode R13 + 0 using a 1-byte displacement ofzero.RIP-relative addressing is enabled by 64-bit mode, not by a 64-bit address-size. Theuse of the address-size prefix does not disable RIP-relative addressing. The effect ofthe address-size prefix is to truncate and zero-extend the computed effectiveaddress to 32 bits.2.2.1.7Default 64-Bit Operand SizeIn 64-bit mode, two groups of instructions have a default operand size of 64 bits (donot need a REX prefix for this operand size).
These are:••Near branchesAll instructions, except far branches, that implicitly reference the RSP2.2.2Additional Encodings for Control and Debug RegistersIn 64-bit mode, more encodings for control and debug registers are available. TheREX.R bit is used to modify the ModR/M reg field when that field encodes a control ordebug register (see Table 2-4). These encodings enable the processor to addressCR8-CR15 and DR8- DR15. An additional control register (CR8) is defined in 64-bitmode. CR8 becomes the Task Priority Register (TPR).In the first implementation of IA-32e mode, CR9-CR15 and DR8-DR15 are not implemented.
Any attempt to access unimplemented registers results in an invalid-opcodeexception (#UD).Vol. 2A 2-15INSTRUCTION FORMAT2-16 Vol. 2ACHAPTER 3INSTRUCTION SET REFERENCE, A-MThis chapter describes the instruction set for the Intel 64 and IA-32 architectures(A-M) in IA-32e, protected, Virtual-8086, and real modes of operation. The setincludes general-purpose, x87 FPU, MMX, SSE/SSE2/SSE3/SSSE3/SSE4,AESNI/PCLMULQDQ, and system instructions.
See also Chapter 4, “Instruction SetReference, N-Z,” in the Intel® 64 and IA-32 Architectures Software Developer’sManual, Volume 2B.For each instruction, each operand combination is described. A description of theinstruction and its operand, an operational description, a description of the effect ofthe instructions on flags in the EFLAGS register, and a summary of exceptions thatcan be generated are also provided.3.1INTERPRETING THE INSTRUCTION REFERENCEPAGESThis section describes the format of information contained in the instruction reference pages in this chapter. It explains notational conventions and abbreviations usedin these sections.3.1.1Instruction FormatThe following is an example of the format used for each instruction description in thischapter.
The heading below introduces the example. The table below provides anexample summary table.CMC—Complement Carry Flag [this is an example]OpcodeInstruction Op/En64-bitModeCompat/Leg ModeDescriptionF5CMCValidValidComplement carry flag.AInstruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANAVol. 2A 3-1INSTRUCTION SET REFERENCE, A-M3.1.1.1Opcode Column in the Instruction Summary TableThe “Opcode” column in the table above shows the object code produced for eachform of the instruction. When possible, codes are given as hexadecimal bytes in thesame order in which they appear in memory.
Definitions of entries other than hexadecimal bytes are as follows:•REX.W — Indicates the use of a REX prefix that affects operand size orinstruction semantics. The ordering of the REX prefix and otheroptional/mandatory instruction prefixes are discussed Chapter 2. Note that REXprefixes that promote legacy instructions to 64-bit behavior are not listedexplicitly in the opcode column.•/digit — A digit between 0 and 7 indicates that the ModR/M byte of theinstruction uses only the r/m (register or memory) operand. The reg fieldcontains the digit that provides an extension to the instruction's opcode.•/r — Indicates that the ModR/M byte of the instruction contains a registeroperand and an r/m operand.•cb, cw, cd, cp, co, ct — A 1-byte (cb), 2-byte (cw), 4-byte (cd), 6-byte (cp),8-byte (co) or 10-byte (ct) value following the opcode.
This value is used tospecify a code offset and possibly a new value for the code segment register.•ib, iw, id, io — A 1-byte (ib), 2-byte (iw), 4-byte (id) or 8-byte (io) immediateoperand to the instruction that follows the opcode, ModR/M bytes or scaleindexing bytes. The opcode determines if the operand is a signed value. Allwords, doublewords and quadwords are given with the low-order byte first.•+rb, +rw, +rd, +ro — A register code, from 0 through 7, added to thehexadecimal byte given at the left of the plus sign to form a single opcode byte.See Table 3-1 for the codes. The +ro columns in the table are applicable only in64-bit mode.•+i — A number used in floating-point instructions when one of the operands isST(i) from the FPU register stack. The number i (which can range from 0 to 7) isadded to the hexadecimal byte given at the left of the plus sign to form a singleopcode byte.Table 3-1.
Register Codes Associated With +rb, +rw, +rd, +roALNone0AXNone0EAXNone0RAXNoneReg FieldREX.Bquadword register(64-Bit Mode only)RegisterReg FieldREX.BRegisterdword registerReg FieldREX.Bword registerRegisterReg FieldREX.BRegisterbyte register0CLNone1CXNone1ECXNone1RCXNone1DLNone2DXNone2EDXNone2RDXNone23-2 Vol. 2AINSTRUCTION SET REFERENCE, A-MTable 3-1. Register Codes Associated With +rb, +rw, +rd, +ro (Contd.)REX.BReg Fieldquadword register(64-Bit Mode only)RegisterReg FieldREX.BRegisterdword registerReg FieldREX.Bword registerRegisterReg FieldREX.BRegisterbyte registerBLNone3BXNone3EBXNone3RBXNone3AHNotencodable(N.E.)4SPNone4ESPNone4N/AN/AN/ACHN.E.5BPNone5EBPNone5N/AN/AN/ADHN.E.6SINone6ESINone6N/AN/AN/ABHN.E.7DINone7EDINone7N/AN/AN/ASPLYes4SPNone4ESPNone4RSPNone4BPLYes5BPNone5EBPNone5RBPNone5SILYes6SINone6ESINone6RSINone6DILYes7DINone7EDINone7RDINone7Registers R8 - R15 (see below): Available in 64-Bit Mode OnlyR8LYes0R8WYes0R8DYes0R8Yes0R9LYes1R9WYes1R9DYes1R9Yes1R10LYes2R10WYes2R10DYes2R10Yes2R11LYes3R11WYes3R11DYes3R11Yes3R12LYes4R12WYes4R12DYes4R12Yes4R13LYes5R13WYes5R13DYes5R13Yes5R14LYes6R14WYes6R14DYes6R14Yes6R15LYes7R15WYes7R15DYes7R15Yes73.1.1.2Instruction Column in the Opcode Summary TableThe “Instruction” column gives the syntax of the instruction statement as it wouldappear in an ASM386 program.
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