Volume 2A Instruction Set Reference A-M (794101), страница 20
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Non-conventionalassignments are described in the “Operation” section. The values of flags listed asundefined may be changed by the instruction in an indeterminate manner. Flagsthat are not listed are unchanged by the instruction.3.1.1.11FPU Flags Affected SectionThe floating-point instructions have an “FPU Flags Affected” section that describeshow each instruction can affect the four condition code flags of the FPU status word.3.1.1.12Protected Mode Exceptions SectionThe “Protected Mode Exceptions” section lists the exceptions that can occur when theinstruction is executed in protected mode and the reasons for the exceptions.
Eachexception is given a mnemonic that consists of a pound sign (#) followed by twoletters and an optional error code in parentheses. For example, #GP(0) denotes ageneral protection exception with an error code of 0. Table 3-3 associates each twoletter mnemonic with the corresponding interrupt vector number and exceptionname. See Chapter 6, “Interrupt and Exception Handling,” in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 3A, for a detailed description ofthe exceptions.Application programmers should consult the documentation provided with their operating systems to determine the actions taken when exceptions occur.Vol.
2A 3-15INSTRUCTION SET REFERENCE, A-MTable 3-3. Intel 64 and IA-32 General ExceptionsVectorNo.Source0#DE—Divide ErrorDIV and IDIV instructions.YesYesYes1#DB—DebugAny code or data reference.YesYesYes3#BP—BreakpointINT 3 instruction.YesYesYes4#OF—OverflowINTO instruction.YesYesYes5#BR—BOUND RangeExceededBOUND instruction.YesYesYes6#UD—InvalidOpcode (UndefinedOpcode)UD2 instruction or reservedopcode.YesYesYes7#NM—Device NotAvailable (No MathCoprocessor)Floating-point or WAIT/FWAITinstruction.YesYesYes8#DF—Double FaultAny instruction that cangenerate an exception, anNMI, or an INTR.YesYesYes10#TS—Invalid TSSTask switch or TSS access.YesReservedYes11#NP—Segment NotPresentLoading segment registers oraccessing system segments.YesReservedYes12#SS—StackSegment FaultStack operations and SSregister loads.YesYesYes13#GP—GeneralProtection2Any memory reference andother protection checks.YesYesYes14#PF—Page FaultAny memory reference.YesReservedYes16#MF—Floating-Point Floating-point or WAIT/FWAITError (Math Fault)instruction.YesYesYes17#AC—AlignmentCheckAny data reference inmemory.YesReservedYes18#MC—MachineCheckModel dependent machinecheck errors.YesYesYes19#XM—SIMDFloating-PointNumeric ErrorSSE/SSE2/SSE3 floating-pointinstructions.YesYesYes3-16 Vol.
2AProtectedMode1RealAddressModeVirtual8086ModeNameINSTRUCTION SET REFERENCE, A-MTable 3-3. Intel 64 and IA-32 General Exceptions (Contd.)VectorNo.NameSourceProtectedMode1Virtual8086ModeRealAddressModeNOTES:1. Apply to protected mode, compatibility mode, and 64-bit mode.2. In the real-address mode, vector 13 is the segment overrun exception.3.1.1.13Real-Address Mode Exceptions SectionThe “Real-Address Mode Exceptions” section lists the exceptions that can occur whenthe instruction is executed in real-address mode (see Table 3-3).3.1.1.14Virtual-8086 Mode Exceptions SectionThe “Virtual-8086 Mode Exceptions” section lists the exceptions that can occur whenthe instruction is executed in virtual-8086 mode (see Table 3-3).3.1.1.15Floating-Point Exceptions SectionThe “Floating-Point Exceptions” section lists exceptions that can occur when an x87FPU floating-point instruction is executed.
All of these exception conditions result ina floating-point error exception (#MF, vector number 16) being generated. Table 3-4associates a one- or two-letter mnemonic with the corresponding exception name.See “Floating-Point Exception Conditions” in Chapter 8 of the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for a detailed description ofthese exceptions.Table 3-4. x87 FPU Floating-Point ExceptionsMnemonicNameSourceFloating-point invalid operation:#IS#IA- Stack overflow or underflow- x87 FPU stack overflow or underflow- Invalid arithmetic operation- Invalid FPU arithmetic operation#ZFloating-point divide-by-zeroDivide-by-zero#DFloating-point denormal operandSource operand that is a denormal number#OFloating-point numeric overflowOverflow in result#UFloating-point numeric underflowUnderflow in result#PFloating-point inexact result(precision)Inexact result (precision)Vol.
2A 3-17INSTRUCTION SET REFERENCE, A-M3.1.1.16SIMD Floating-Point Exceptions SectionThe “SIMD Floating-Point Exceptions” section lists exceptions that can occur when anSSE/SSE2/SSE3 floating-point instruction is executed. All of these exception conditions result in a SIMD floating-point error exception (#XM, vector number 19) beinggenerated. Table 3-5 associates a one-letter mnemonic with the correspondingexception name.
For a detailed description of these exceptions, refer to ”SSE andSSE2 Exceptions”, in Chapter 11 of the Intel® 64 and IA-32 Architectures SoftwareDeveloper’s Manual, Volume 1.Table 3-5. SIMD Floating-Point ExceptionsMnemonicNameSource#IFloating-point invalid operationInvalid arithmetic operation or source operand#ZFloating-point divide-by-zeroDivide-by-zero#DFloating-point denormal operandSource operand that is a denormal number#OFloating-point numeric overflowOverflow in result#UFloating-point numeric underflow Underflow in result#PFloating-point inexact result3.1.1.17Inexact result (precision)Compatibility Mode Exceptions SectionThis section lists exceptions that occur within compatibility mode.3.1.1.1864-Bit Mode Exceptions SectionThis section lists exceptions that occur within 64-bit mode.3.2INSTRUCTIONS (A-M)The remainder of this chapter provides descriptions of Intel 64 and IA-32 instructions(A-M).
See also: Chapter 4, “Instruction Set Reference, N-Z,” in the Intel® 64 andIA-32 Architectures Software Developer’s Manual, Volume 2B.3-18 Vol. 2AINSTRUCTION SET REFERENCE, A-MAAA—ASCII Adjust After AdditionOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode37AAAAInvalidValidASCII adjust AL afteraddition.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionAdjusts the sum of two unpacked BCD values to create an unpacked BCD result. TheAL register is the implied source and destination operand for this instruction.
The AAAinstruction is only useful when it follows an ADD instruction that adds (binary addition) two unpacked BCD values and stores a byte result in the AL register. The AAAinstruction then adjusts the contents of the AL register to contain the correct 1-digitunpacked BCD result.If the addition produces a decimal carry, the AH register increments by 1, and the CFand AF flags are set. If there was no decimal carry, the CF and AF flags are clearedand the AH register is unchanged. In either case, bits 4 through 7 of the AL registerare set to 0.This instruction executes as described in compatibility mode and legacy mode.
It isnot valid in 64-bit mode.OperationIF 64-Bit ModeTHEN#UD;ELSEIF ((AL AND 0FH) > 9) or (AF = 1)THENAL ← AL + 6;AH ← AH + 1;AF ← 1;CF ← 1;AL ← AL AND 0FH;ELSEAF ← 0;CF ← 0;AL ← AL AND 0FH;FI;AAA—ASCII Adjust After AdditionVol. 2A 3-19INSTRUCTION SET REFERENCE, A-MFI;Flags AffectedThe AF and CF flags are set to 1 if the adjustment results in a decimal carry; otherwise they are set to 0. The OF, SF, ZF, and PF flags are undefined.Protected Mode Exceptions#UDIf the LOCK prefix is used.Real-Address Mode ExceptionsSame exceptions as protected mode.Virtual-8086 Mode ExceptionsSame exceptions as protected mode.Compatibility Mode ExceptionsSame exceptions as protected mode.64-Bit Mode Exceptions#UD3-20 Vol.
2AIf in 64-bit mode.AAA—ASCII Adjust After AdditionINSTRUCTION SET REFERENCE, A-MAAD—ASCII Adjust AX Before DivisionOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg ModeD5 0AAADAInvalidValidASCII adjust AX beforedivision.D5 ib(No mnemonic)AInvalidValidAdjust AX before division tonumber base imm8.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4ANANANANADescriptionAdjusts two unpacked BCD digits (the least-significant digit in the AL register and themost-significant digit in the AH register) so that a division operation performed onthe result will yield a correct unpacked BCD value.
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