Volume 2A Instruction Set Reference A-M (794101), страница 23
Текст из файла (страница 23)
2A 3-37INSTRUCTION SET REFERENCE, A-MIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)3-38 Vol.
2AIf a memory address referencing the SS segment is in a noncanonical form.ADDPS—Add Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.ADDPS—Add Packed Single-Precision Floating-Point ValuesVol.
2A 3-39INSTRUCTION SET REFERENCE, A-MADDSD—Add Scalar Double-Precision Floating-Point ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg ModeF2 0F 58 /rADDSD xmm1,xmm2/m64AValidValidAdd the low doubleprecision floating-pointvalue from xmm2/m64 toxmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionAdds the low double-precision floating-point values from the source operand (secondoperand) and the destination operand (first operand), and stores the double-precision floating-point result in the destination operand.The source operand can be an XMM register or a 64-bit memory location.
The destination operand is an XMM register. The high quadword of the destination operandremains unchanged. See Chapter 11 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an overview of a scalar double-precisionfloating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← DEST[63:0] + SRC[63:0];(* DEST[127:64] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentADDSD__m128d _mm_add_sd (m128d a, m128d b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.3-40 Vol.
2AADDSD—Add Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.ADDSD—Add Scalar Double-Precision Floating-Point ValuesVol.
2A 3-41INSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.#AC(0)3-42 Vol. 2AIf alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.ADDSD—Add Scalar Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MADDSS—Add Scalar Single-Precision Floating-Point ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg ModeF3 0F 58 /rADDSS xmm1,xmm2/m32AValidValidAdd the low single-precisionfloating-point value fromxmm2/m32 to xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionAdds the low single-precision floating-point values from the source operand (secondoperand) and the destination operand (first operand), and stores the single-precisionfloating-point result in the destination operand.The source operand can be an XMM register or a 32-bit memory location.
The destination operand is an XMM register. The three high-order doublewords of the destination operand remain unchanged. See Chapter 10 in the Intel® 64 and IA-32Architectures Software Developer’s Manual, Volume 1, for an overview of a scalarsingle-precision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← DEST[31:0] + SRC[31:0];(* DEST[127:32] unchanged *)Intel C/C++ Compiler Intrinsic EquivalentADDSS__m128 _mm_add_ss(__m128 a, __m128 b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.ADDSS—Add Scalar Single-Precision Floating-Point ValuesVol.
2A 3-43INSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode ExceptionsGPIf any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)For a page fault.3-44 Vol.
2AADDSS—Add Scalar Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.ADDSS—Add Scalar Single-Precision Floating-Point ValuesVol. 2A 3-45INSTRUCTION SET REFERENCE, A-MADDSUBPD—Packed Double-FP Add/SubtractOpcodeInstructionOp/En66 0F D0 /rADDSUBPD xmm1, Axmm2/m12864-bitModeCompat/ DescriptionLeg ModeValidValidAdd/subtract doubleprecision floating-pointvalues from xmm2/m128 toxmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionAdds the double-precision floating-point values in the high quadword of the sourceand destination operands and stores the result in the high quadword of the destination operand.Subtracts the double-precision floating-point value in the low quadword of the sourceoperand from the low quadword of the destination operand and stores the result inthe low quadword of the destination operand.
See Figure 3-3.The source operand can be a 128-bit memory location or an XMM register. The destination operand is an XMM register.$''68%3'[PP[PPP>@>@[PP>@[PPP>@[PP>@[PPP>@>@>@[PPP5(68/7[PP20Figure 3-3. ADDSUBPD—Packed Double-FP Add/Subtract3-46 Vol. 2AADDSUBPD—Packed Double-FP Add/SubtractINSTRUCTION SET REFERENCE, A-MIn 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).Operationxmm1[63:0] = xmm1[63:0] - xmm2/m128[63:0];xmm1[127:64] = xmm1[127:64] + xmm2/m128[127:64];Intel C/C++ Compiler Intrinsic EquivalentADDSUBPD__m128d _mm_addsub_pd(__m128d a, __m128d b)ExceptionsWhen the source operand is a memory operand, it must be aligned on a 16-byteboundary or a general-protection exception (#GP) will be generated.SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMFor an unmasked Streaming SIMD Extensions numeric exception, CR4.OSXMMEXCPT[bit 10] = 1.#UDIf CR0.EM is 1.For an unmasked Streaming SIMD Extensions numeric exception (CR4.OSXMMEXCPT[bit 10] = 0).If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE3[bit 0] = 0.If the LOCK prefix is used.Real Address Mode ExceptionsGP(0)If any part of the operand would lie outside of the effectiveaddress space from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.ADDSUBPD—Packed Double-FP Add/SubtractVol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
