Volume 2A Instruction Set Reference A-M (794101), страница 22
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2A 3-29INSTRUCTION SET REFERENCE, A-M64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.3-30 Vol.
2AADC—Add with CarryINSTRUCTION SET REFERENCE, A-MADD—AddOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode04 ibADD AL, imm8CValidValidAdd imm8 to AL.05 iwADD AX, imm16CValidValidAdd imm16 to AX.05 idADD EAX, imm32CValidValidAdd imm32 to EAX.REX.W + 05 idADD RAX, imm32CValidN.E.Add imm32 sign-extendedto 64-bits to RAX.80 /0 ibADD r/m8, imm8BValidValidAdd imm8 to r/m8.*REX + 80 /0 ibADD r/m8 , imm8BValidN.E.Add sign-extended imm8 tor/m64.81 /0 iwADD r/m16,imm16BValidValidAdd imm16 to r/m16.81 /0 idADD r/m32,imm32BValidValidAdd imm32 to r/m32.REX.W + 81 /0idADD r/m64,imm32BValidN.E.Add imm32 sign-extendedto 64-bits to r/m64.83 /0 ibADD r/m16, imm8 BValidValidAdd sign-extended imm8 tor/m16.83 /0 ibADD r/m32, imm8 BValidValidAdd sign-extended imm8 tor/m32.REX.W + 83 /0ibADD r/m64, imm8 BValidN.E.Add sign-extended imm8 tor/m64.00 /rADD r/m8, r8AValidValidAdd r8 to r/m8.REX + 00 /rADD r/m8*, r8*AValidN.E.Add r8 to r/m8.01 /rADD r/m16, r16AValidValidAdd r16 to r/m16.01 /rADD r/m32, r32AValidValidAdd r32 to r/m32.REX.W + 01 /rADD r/m64, r64AValidN.E.Add r64 to r/m64.02 /rADD r8, r/m8AValidValidAdd r/m8 to r8.REX + 02 /rADD r8*, r/m8*AValidN.E.Add r/m8 to r8.03 /rADD r16, r/m16AValidValidAdd r/m16 to r16.03 /rADD r32, r/m32AValidValidAdd r/m32 to r32.REX.W + 03 /rADD r64, r/m64AValidN.E.Add r/m64 to r64.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.ADD—AddVol.
2A 3-31INSTRUCTION SET REFERENCE, A-MInstruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANABModRM:r/m (r, w)imm8NANACAL/AX/EAX/RAXimm8NANADescriptionAdds the destination operand (first operand) and the source operand (secondoperand) and then stores the result in the destination operand. The destinationoperand can be a register or a memory location; the source operand can be an immediate, a register, or a memory location. (However, two memory operands cannot beused in one instruction.) When an immediate value is used as an operand, it is signextended to the length of the destination operand format.The ADD instruction performs integer addition.
It evaluates the result for both signedand unsigned integer operands and sets the OF and CF flags to indicate a carry (overflow) in the signed or unsigned result, respectively. The SF flag indicates the sign ofthe signed result.This instruction can be used with a LOCK prefix to allow the instruction to beexecuted atomically.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15).
Using a REX aREX prefix in the form of REX.W promotes operation to 64 bits. See the summarychart at the beginning of this section for encoding data and limits.OperationDEST ← DEST + SRC;Flags AffectedThe OF, SF, ZF, AF, CF, and PF flags are set according to the result.Protected Mode Exceptions#GP(0)If the destination is located in a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register is used to access memory and itcontains a NULL segment selector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.3-32 Vol. 2AADD—AddINSTRUCTION SET REFERENCE, A-M#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.ADD—AddVol.
2A 3-33INSTRUCTION SET REFERENCE, A-MADDPD—Add Packed Double-Precision Floating-Point ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 58 /rADDPD xmm1,xmm2/m128AValidValidAdd packed double-precisionfloating-point values fromxmm2/m128 to xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionPerforms a SIMD add of the two packed double-precision floating-point values fromthe source operand (second operand) and the destination operand (first operand),and stores the packed double-precision floating-point results in the destinationoperand.The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. See Chapter 11 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an overview of SIMD doubleprecision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[63:0] ← DEST[63:0] + SRC[63:0];DEST[127:64] ← DEST[127:64] + SRC[127:64];Intel C/C++ Compiler Intrinsic EquivalentADDPD__m128d _mm_add_pd (m128d a, m128d b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)3-34 Vol.
2AFor an illegal address in the SS segment.ADDPD—Add Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.ADDPD—Add Packed Double-Precision Floating-Point ValuesVol.
2A 3-35INSTRUCTION SET REFERENCE, A-M#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#XMIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 1.#UDIf an unmasked SIMD floating-point exception and CR4.OSXMMEXCPT[bit 10] = 0.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.3-36 Vol. 2AADDPD—Add Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MADDPS—Add Packed Single-Precision Floating-Point ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F 58 /rADDPS xmm1,xmm2/m128AValidValidAdd packed single-precisionfloating-point values fromxmm2/m128 to xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionPerforms a SIMD add of the four packed single-precision floating-point values fromthe source operand (second operand) and the destination operand (first operand),and stores the packed single-precision floating-point results in the destinationoperand.The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register. See Chapter 10 in the Intel® 64 and IA-32 Architectures Software Developer’s Manual, Volume 1, for an overview of SIMD singleprecision floating-point operation.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[31:0] ← DEST[31:0] + SRC[31:0];DEST[63:32] ← DEST[63:32] + SRC[63:32];DEST[95:64] ← DEST[95:64] + SRC[95:64];DEST[127:96] ← DEST[127:96] + SRC[127:96];Intel C/C++ Compiler Intrinsic EquivalentADDPS__m128 _mm_add_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsOverflow, Underflow, Invalid, Precision, Denormal.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.ADDPS—Add Packed Single-Precision Floating-Point ValuesVol.
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