Volume 2A Instruction Set Reference A-M (794101), страница 26
Текст из файла (страница 26)
2A 3-67INSTRUCTION SET REFERENCE, A-MAESKEYGENASSIST—AES Round Key Generation AssistOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 3A DF /ribAESKEYGENASSIST xmm1,xmm2/m128,imm8AValidValidAssist in AES round key generation using an 8 bitsRound Constant (RCON)specified in the immediatebyte, operating on 128 bitsof data specified inxmm2/m128 and stores theresult in xmm1.Instruction Operand EncodingOp/EnOperand 1Operand2Operand3Operand4AModRM:reg (w)ModRM:r/m (r)imm8NADescriptionAssist in expanding the AES cipher key, by computing steps towards generating around key for encryption, using 128-bit data specified in the source operand and an8-bit round constant specified as an immediate, store the result in the destinationoperand.The destination operand is an XMM register.
The source operand can be an XMMregister or a 128-bit memory location.OperationX3[31:0] ← SRC [127: 96];X2[31:0] ← SRC [95: 64];X1[31:0] ← SRC [63: 32];X0[31:0] ← SRC [31: 0];RCON[31:0] ← ZeroExtend(Imm8[7:0]);DEST[31:0] ← SubWord(X1);DEST[63:32 ] ← RotWord( SubWord(X1) ) XOR RCON;DEST[95:64] ← SubWord(X3);DEST[127:96] ← RotWord( SubWord(X3) ) XOR RCON;DEST[255:128] (Unmodified)Intel C/C++ Compiler Intrinsic EquivalentAESKEYGENASSIST __m128i _mm_aesimc (__m128i, const int)3-68 Vol. 2AAESKEYGENASSIST—AES Round Key Generation AssistINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.AESKEYGENASSIST—AES Round Key Generation AssistVol.
2A 3-69INSTRUCTION SET REFERENCE, A-MIf memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.AESNI[bit 25] = 0.If the LOCK prefix is used.3-70 Vol. 2AAESKEYGENASSIST—AES Round Key Generation AssistINSTRUCTION SET REFERENCE, A-MAND—Logical ANDOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode24 ibAND AL, imm8CValidValidAL AND imm8.25 iwAND AX, imm16CValidValidAX AND imm16.25 idAND EAX, imm32CValidValidEAX AND imm32.REX.W + 25 idAND RAX, imm32CValidN.E.RAX AND imm32 signextended to 64-bits.80 /4 ibAND r/m8, imm8BValidValidr/m8 AND imm8.*REX + 80 /4 ibAND r/m8 , imm8BValidN.E.r/m64 AND imm8 (signextended).81 /4 iwAND r/m16,imm16BValidValidr/m16 AND imm16.81 /4 idAND r/m32,imm32BValidValidr/m32 AND imm32.REX.W + 81 /4idAND r/m64,imm32BValidN.E.r/m64 AND imm32 signextended to 64-bits.83 /4 ibAND r/m16, imm8 BValidValidr/m16 AND imm8 (signextended).83 /4 ibAND r/m32, imm8 BValidValidr/m32 AND imm8 (signextended).REX.W + 83 /4ibAND r/m64, imm8 BValidN.E.r/m64 AND imm8 (signextended).20 /rAND r/m8, r8AValidValidr/m8 AND r8.REX + 20 /rAND r/m8*, r8*AValidN.E.r/m64 AND r8 (signextended).21 /rAND r/m16, r16AValidValidr/m16 AND r16.21 /rAND r/m32, r32AValidValidr/m32 AND r32.REX.W + 21 /rAND r/m64, r64AValidN.E.r/m64 AND r32.22 /rAND r8, r/m8AValidValidr8 AND r/m8.**REX + 22 /rAND r8 , r/m8AValidN.E.r/m64 AND r8 (signextended).23 /rAND r16, r/m16AValidValidr16 AND r/m16.23 /rAND r32, r/m32AValidValidr32 AND r/m32.REX.W + 23 /rAND r64, r/m64AValidN.E.r64 AND r/m64.NOTES:*In 64-bit mode, r/m8 can not be encoded to access the following byte registers if a REX prefix isused: AH, BH, CH, DH.AND—Logical ANDVol.
2A 3-71INSTRUCTION SET REFERENCE, A-MInstruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANABModRM:r/m (r, w)imm8NANACAL/AX/EAX/RAXimm8NANADescriptionPerforms a bitwise AND operation on the destination (first) and source (second)operands and stores the result in the destination operand location.
The sourceoperand can be an immediate, a register, or a memory location; the destinationoperand can be a register or a memory location. (However, two memory operandscannot be used in one instruction.) Each bit of the result is set to 1 if both corresponding bits of the first and second operands are 1; otherwise, it is set to 0.This instruction can be used with a LOCK prefix to allow the it to be executed atomically.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15).
Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationDEST ← DEST AND SRC;Flags AffectedThe OF and CF flags are cleared; the SF, ZF, and PF flags are set according to theresult. The state of the AF flag is undefined.Protected Mode Exceptions#GP(0)If the destination operand points to a non-writable segment.If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.3-72 Vol.
2AAND—Logical ANDINSTRUCTION SET REFERENCE, A-M#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used but the destination is not a memoryoperand.AND—Logical ANDVol.
2A 3-73INSTRUCTION SET REFERENCE, A-MANDPD—Bitwise Logical AND of Packed Double-Precision FloatingPoint ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 54 /rANDPD xmm1,xmm2/m128AValidValidBitwise logical AND ofxmm2/m128 and xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionPerforms a bitwise logical AND of the two packed double-precision floating-pointvalues from the source operand (second operand) and the destination operand (firstoperand), and stores the result in the destination operand.The source operand can be an XMM register or a 128-bit memory location.
The destination operand is an XMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[127:0] ← DEST[127:0] BitwiseAND SRC[127:0];Intel C/C++ Compiler Intrinsic EquivalentANDPD__m128d _mm_and_pd(__m128d a, __m128d b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.3-74 Vol. 2AANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NM#UDIf CR0.TS[bit 3] = 1.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE2[bit 26] = 0.If the LOCK prefix is used.ANDPD—Bitwise Logical AND of Packed Double-Precision Floating-Point ValuesVol.
2A 3-75INSTRUCTION SET REFERENCE, A-MANDPS—Bitwise Logical AND of Packed Single-Precision Floating-PointValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F 54 /rANDPS xmm1,xmm2/m128AValidValidBitwise logical AND ofxmm2/m128 and xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)NANADescriptionPerforms a bitwise logical AND of the four packed single-precision floating-pointvalues from the source operand (second operand) and the destination operand (firstoperand), and stores the result in the destination operand.The source operand can be an XMM register or a 128-bit memory location. The destination operand is an XMM register.In 64-bit mode, using a REX prefix in the form of REX.R permits this instruction toaccess additional registers (XMM8-XMM15).OperationDEST[127:0] ← DEST[127:0] BitwiseAND SRC[127:0];Intel C/C++ Compiler Intrinsic EquivalentANDPS__m128 _mm_and_ps(__m128 a, __m128 b)SIMD Floating-Point ExceptionsNone.Protected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.3-76 Vol.
2AANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-M#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.If any part of the operand lies outside the effective addressspace from 0 to FFFFH.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.Virtual-8086 Mode ExceptionsSame exceptions as in real address mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.If memory operand is not aligned on a 16-byte boundary,regardless of segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:EDX.SSE[bit 25] = 0.If the LOCK prefix is used.ANDPS—Bitwise Logical AND of Packed Single-Precision Floating-Point ValuesVol.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
