Volume 2A Instruction Set Reference A-M (794101), страница 28
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The mask bits are bits [1:0] of the immediate byte(third operand). Each mask bit corresponds to a quadword element in a 128-bitoperand.If a mask bit is “1", then the corresponding quadword in the source operand is copiedto the destination, else the quadword element in the destination operand is leftunchanged.OperationIF (imm8[0] == 1)THEN DEST[63:0] Å SRC[63:0];ELSE DEST[63:0] Å DEST[63:0]; FI;IF (imm8[1] == 1)THEN DEST[127:64] Å SRC[127:64];ELSE DEST[127:64] Å DEST[127:64]; FI;Intel C/C++ Compiler Intrinsic EquivalentBLENDPD__m128d _mm_blend_pd (__m128d v1, __m128d v2, const int mask);SIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS, or GS segments.BLENDPD — Blend Packed Double Precision Floating-Point ValuesVol.
2A 3-85INSTRUCTION SET REFERENCE, A-MIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Real Mode Exceptions#GP(0)If any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in Protected Mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#PF(fault-code)For a page fault.#NMIf TS in CR0 is set.#UDIf EM in CR0 is set.3-86 Vol.
2ABLENDPD — Blend Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf OSFXSR in CR4 is 0.If CPUID feature flag ECX.SSE4_1 is 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.BLENDPD — Blend Packed Double Precision Floating-Point ValuesVol. 2A 3-87INSTRUCTION SET REFERENCE, A-MBLENDPS — Blend Packed Single Precision Floating-Point ValuesOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode66 0F 3A 0C /ribBLENDPS xmm1,xmm2/m128,imm8AValidValidSelect packed singleprecision floating-pointvalues from xmm1 andxmm2/m128 from maskspecified in imm8 and storethe values into xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)imm8NADescriptionPacked single-precision floating-point values from the source operand (secondoperand) are conditionally copied to the destination operand (first operand)depending on the mask bits in the immediate operand. The mask bits are bits [3:0]of the immediate byte (third operand).
Each mask bit corresponds to a dwordelement in a 128-bit operand.If a mask bit is “1", then the corresponding dword in the source operand is copied tothe destination, else the dword element in the destination operand is left unchanged.OperationIF (imm8[0] == 1)THEN DEST[31:0] Å SRC[31:0];ELSE DEST[31:0] Å DEST[31:0]; FI;IF (imm8[1] == 1)THEN DEST[63:32] Å SRC[63:32];ELSE DEST[63:32] Å DEST[63:32]; FI;IF (imm8[2] == 1)THEN DEST[95:64] Å SRC[95:64];ELSE DEST[95:64] Å DEST[95:64]; FI;IF (imm8[3] == 1)THEN DEST[127:96] Å SRC[127:96];ELSE DEST[127:96] Å DEST[127:96]; FI;Intel C/C++ Compiler Intrinsic EquivalentBLENDPS3-88 Vol. 2A__m128 _mm_blend_ps (__m128 v1, __m128 v2, const int mask);BLENDPS — Blend Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS, or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Real Mode Exceptions#GP(0)if any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.#NMIf CR0.TS[bit 3] = 1.If not aligned on 16-byte boundary, regardless of segment#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in Protected Mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.If not aligned on 16-byte boundary, regardless of segmentBLENDPS — Blend Packed Single Precision Floating-Point ValuesVol.
2A 3-89INSTRUCTION SET REFERENCE, A-M#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#PF(fault-code)For a page fault.#NMIf TS in CR0 is set.#UDIf EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag ECX.SSE4_1 is 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.3-90 Vol. 2ABLENDPS — Blend Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MBLENDVPD — Variable Blend Packed Double Precision Floating-PointValuesOpcodeInstructionOp/En66 0F 38 15 /rBLENDVPD xmm1, Axmm2/m128 ,<XMM0>64-bitModeCompat/ DescriptionLeg ModeValidValidSelect packed DP FP valuesfrom xmm1 and xmm2 frommask specified in XMM0 andstore the values in xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)implicit XMM0NADescriptionPacked double-precision floating-point values from the source operand (second argument) are conditionally copied to the destination operand (first argument) dependingon the mask bits in the implicit third register argument, XMM0.
The mask bits are themost significant bit in each qword element of XMM0. Each mask bit corresponds to aquadword element in a 128-bit operand.If a mask bit is “1", then the corresponding quadword element in the source operandis copied to the destination, else the quadword element in the destination operand isleft unchanged.The register assignment of the third operand is defined to be the architecturalregister XMM0.OperationMASK Å XMM0;IF (MASK[63] == 1)THEN DEST[63:0] Å SRC[63:0];ELSE DEST[63:0] Å DEST[63:0]; FI;IF (MASK[127] == 1)THEN DEST[127:64] Å SRC[127:64];ELSE DEST[127:64] Å DEST[127:64]; FI;Intel C/C++ Compiler Intrinsic EquivalentBLENDVPD__m128d _mm_blendv_pd(__m128d v1, __m128d v2, __m128d v3);BLENDVPD — Variable Blend Packed Double Precision Floating-Point ValuesVol.
2A 3-91INSTRUCTION SET REFERENCE, A-MSIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS, or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Real Mode Exceptions#GP(0)if any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode.#PF(fault-code)For a page fault.Compatibility Mode ExceptionsSame exceptions as in Protected Mode.64-Bit Mode Exceptions#GP(0)3-92 Vol.
2AIf the memory address is in a non-canonical form.BLENDVPD — Variable Blend Packed Double Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MIf a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#PF(fault-code)For a page fault.#NMIf TS in CR0 is set.#UDIf EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag ECX.SSE4_1 is 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.BLENDVPD — Variable Blend Packed Double Precision Floating-Point ValuesVol.
2A 3-93INSTRUCTION SET REFERENCE, A-MBLENDVPS — Variable Blend Packed Single Precision Floating-PointValuesOpcodeInstructionOp/En66 0F 38 14 /rBLENDVPS xmm1, Axmm2/m128,<XMM0>64-bitModeCompat/ DescriptionLeg ModeValidValidSelect packed singleprecision floating-pointvalues from xmm1 andxmm2/m128 from maskspecified in XMM0 and storethe values into xmm1.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r, w)ModRM:r/m (r)implicit XMM0NADescriptionPacked single-precision floating-point values from the source operand (second argument) are conditionally written to the destination operand (first argument)depending on the mask bits in the third register argument.
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