Volume 2A Instruction Set Reference A-M (794101), страница 29
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The mask bits are themost significant bit in each dword element of XMM0. Each mask bit corresponds to adword element in a 128-bit operand.If a mask bit is “1", then the corresponding dword element in the source operand iscopied to the destination, else the dword element in the destination operand is leftunchanged.The register assignment of the third operand is defined to be the architecturalregister XMM0.OperationMASK Å XMM0;IF (MASK[31] == 1)THEN DEST[31:0] Å SRC[31:0];ELSE DEST[31:0] Å DEST[31:0]); FI;IF (MASK[63] == 1)THEN DEST[63:32] Å SRC[63:32]);ELSE DEST[63:32] Å DEST[63:32]); FI;IF (MASK[95] == 1)THEN DEST[95:64] Å SRC[95:64]);ELSE DEST[95:64] Å DEST[95:64]); FI;IF (MASK[127] == 1)THEN DEST[127:96] Å SRC[127:96]);3-94 Vol.
2ABLENDVPS — Variable Blend Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MELSE DEST[127:96] Å DEST[127:96]); FI;Intel C/C++ Compiler Intrinsic EquivalentBLENDVPS __m128 _mm_blendv_ps(__m128 v1, __m128 v2, __m128 v3);SIMD Floating-Point ExceptionsNoneProtected Mode Exceptions#GP(0)For an illegal memory operand effective address in the CS, DS,ES, FS, or GS segments.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)For an illegal address in the SS segment.#PF(fault-code)For a page fault.#NMIf CR0.TS[bit 3] = 1.#UDIf CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Real Mode Exceptions#GP(0)if any part of the operand lies outside of the effective addressspace from 0 to 0FFFFH.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#NM#UDIf CR0.TS[bit 3] = 1.If CR0.EM[bit 2] = 1.If CR4.OSFXSR[bit 9] = 0.If CPUID.01H:ECX.SSE4_1[bit 19] = 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.Virtual 8086 Mode ExceptionsSame exceptions as in Real Address Mode.#PF(fault-code)For a page fault.BLENDVPS — Variable Blend Packed Single Precision Floating-Point ValuesVol.
2A 3-95INSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in Protected Mode.64-Bit Mode Exceptions#GP(0)If the memory address is in a non-canonical form.If a memory operand is not aligned on a 16-byte boundary,regardless of segment.#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#PF(fault-code)For a page fault.#NMIf TS in CR0 is set.#UDIf EM in CR0 is set.If OSFXSR in CR4 is 0.If CPUID feature flag ECX.SSE4_1 is 0.If LOCK prefix is used.Either the prefix REP (F3h) or REPN (F2H) is used.3-96 Vol.
2ABLENDVPS — Variable Blend Packed Single Precision Floating-Point ValuesINSTRUCTION SET REFERENCE, A-MBOUND—Check Array Index Against BoundsOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode62 /rBOUND r16,m16&16AInvalidValidCheck if r16 (array index) iswithin bounds specified bym16&16.62 /rBOUND r32,m32&32AInvalidValidCheck if r32 (array index) iswithin bounds specified bym16&16.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (r)ModRM:r/m (r)NANADescriptionBOUND determines if the first operand (array index) is within the bounds of an arrayspecified the second operand (bounds operand).
The array index is a signed integerlocated in a register. The bounds operand is a memory location that contains a pair ofsigned doubleword-integers (when the operand-size attribute is 32) or a pair ofsigned word-integers (when the operand-size attribute is 16). The first doubleword(or word) is the lower bound of the array and the second doubleword (or word) is theupper bound of the array. The array index must be greater than or equal to the lowerbound and less than or equal to the upper bound plus the operand size in bytes.
If theindex is not within bounds, a BOUND range exceeded exception (#BR) is signaled.When this exception is generated, the saved return instruction pointer points to theBOUND instruction.The bounds limit data structure (two words or doublewords containing the lower andupper limits of the array) is usually placed just before the array itself, making thelimits addressable via a constant offset from the beginning of the array. Because theaddress of the array already will be present in a register, this practice avoids extrabus cycles to obtain the effective address of the array bounds.This instruction executes as described in compatibility mode and legacy mode.
It isnot valid in 64-bit mode.OperationIF 64bit ModeTHEN#UD;ELSEIF (ArrayIndex < LowerBound OR ArrayIndex > UpperBound)(* Below lower bound or above upper bound *)BOUND—Check Array Index Against BoundsVol. 2A 3-97INSTRUCTION SET REFERENCE, A-MTHEN #BR; FI;FI;Flags AffectedNone.Protected Mode Exceptions#BRIf the bounds test fails.#UDIf second operand is not a memory location.If the LOCK prefix is used.#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.Real-Address Mode Exceptions#BRIf the bounds test fails.#UDIf second operand is not a memory location.#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.If the LOCK prefix is used.Virtual-8086 Mode Exceptions#BRIf the bounds test fails.#UDIf second operand is not a memory location.If the LOCK prefix is used.#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.3-98 Vol.
2ABOUND—Check Array Index Against BoundsINSTRUCTION SET REFERENCE, A-MCompatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#UDIf in 64-bit mode.BOUND—Check Array Index Against BoundsVol. 2A 3-99INSTRUCTION SET REFERENCE, A-MBSF—Bit Scan ForwardOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F BC /rBSF r16, r/m16AValidValidBit scan forward on r/m16.0F BC /rBSF r32, r/m32AValidValidBit scan forward on r/m32.REX.W + 0F BCBSF r64, r/m64AValidN.E.Bit scan forward on r/m64.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionSearches the source operand (second operand) for the least significant set bit (1 bit).If a least significant 1 bit is found, its bit index is stored in the destination operand(first operand).
The source operand can be a register or a memory location; thedestination operand is a register. The bit index is an unsigned offset from bit 0 of thesource operand. If the content of the source operand is 0, the content of the destination operand is undefined.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationIF SRC = 0THENZF ← 1;DEST is undefined;ELSEZF ← 0;temp ← 0;WHILE Bit(SRC, temp) = 0DOtemp ← temp + 1;DEST ← temp;OD;FI;3-100 Vol. 2ABSF—Bit Scan ForwardINSTRUCTION SET REFERENCE, A-MFlags AffectedThe ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared.The CF, OF, SF, AF, and PF, flags are undefined.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.BSF—Bit Scan ForwardVol.
2A 3-101INSTRUCTION SET REFERENCE, A-M#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-102 Vol. 2ABSF—Bit Scan ForwardINSTRUCTION SET REFERENCE, A-MBSR—Bit Scan ReverseOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F BD /rBSR r16, r/m16AValidValidBit scan reverse on r/m16.0F BD /rBSR r32, r/m32AValidValidBit scan reverse on r/m32.REX.W + 0F BDBSR r64, r/m64AValidN.E.Bit scan reverse on r/m64.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:reg (w)ModRM:r/m (r)NANADescriptionSearches the source operand (second operand) for the most significant set bit (1 bit).If a most significant 1 bit is found, its bit index is stored in the destination operand(first operand).
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