Volume 2A Instruction Set Reference A-M (794101), страница 30
Текст из файла (страница 30)
The source operand can be a register or a memory location; thedestination operand is a register. The bit index is an unsigned offset from bit 0 of thesource operand. If the content source operand is 0, the content of the destinationoperand is undefined.In 64-bit mode, the instruction’s default operation size is 32 bits.
Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.OperationIF SRC = 0THENZF ← 1;DEST is undefined;ELSEZF ← 0;temp ← OperandSize – 1;WHILE Bit(SRC, temp) = 0DOtemp ← temp - 1;DEST ← temp;OD;FI;BSR—Bit Scan ReverseVol.
2A 3-103INSTRUCTION SET REFERENCE, A-MFlags AffectedThe ZF flag is set to 1 if all the source operand is 0; otherwise, the ZF flag is cleared.The CF, OF, SF, AF, and PF, flags are undefined.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.Virtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.3-104 Vol.
2ABSR—Bit Scan ReverseINSTRUCTION SET REFERENCE, A-M#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.BSR—Bit Scan ReverseVol. 2A 3-105INSTRUCTION SET REFERENCE, A-MBSWAP—Byte SwapOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F C8+rdBSWAP r32AValid*ValidReverses the byte order ofa 32-bit register.REX.W + 0FC8+rdBSWAP r64AValidN.E.Reverses the byte order ofa 64-bit register.NOTES:* See IA-32 Architecture Compatibility section below.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4Areg (r, w)NANANADescriptionReverses the byte order of a 32-bit or 64-bit (destination) register.
This instruction isprovided for converting little-endian values to big-endian format and vice versa. Toswap bytes in a word value (16-bit register), use the XCHG instruction. When theBSWAP instruction references a 16-bit register, the result is undefined.In 64-bit mode, the instruction’s default operation size is 32 bits. Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15).
Using a REXprefix in the form of REX.W promotes operation to 64 bits. See the summary chart atthe beginning of this section for encoding data and limits.IA-32 Architecture Legacy CompatibilityThe BSWAP instruction is not supported on IA-32 processors earlier than theIntel486™ processor family. For compatibility with this instruction, softwareshould include functionally equivalent code for execution on Intel processors earlierthan the Intel486 processor family.OperationTEMP ← DESTIF 64-bit mode AND OperandSize = 64THENDEST[7:0] ← TEMP[63:56];DEST[15:8] ← TEMP[55:48];DEST[23:16] ← TEMP[47:40];DEST[31:24] ← TEMP[39:32];DEST[39:32] ← TEMP[31:24];3-106 Vol.
2ABSWAP—Byte SwapINSTRUCTION SET REFERENCE, A-MDEST[47:40] ← TEMP[23:16];DEST[55:48] ← TEMP[15:8];DEST[63:56] ← TEMP[7:0];ELSEDEST[7:0] ← TEMP[31:24];DEST[15:8] ← TEMP[23:16];DEST[23:16] ← TEMP[15:8];DEST[31:24] ← TEMP[7:0];FI;Flags AffectedNone.Exceptions (All Operating Modes)#UDBSWAP—Byte SwapIf the LOCK prefix is used.Vol. 2A 3-107INSTRUCTION SET REFERENCE, A-MBT—Bit TestOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F A3BT r/m16, r16AValidValidStore selected bit in CF flag.0F A3BT r/m32, r32AValidValidStore selected bit in CF flag.REX.W + 0F A3BT r/m64, r64AValidN.E.Store selected bit in CF flag.0F BA /4 ibBT r/m16, imm8BValidValidStore selected bit in CF flag.0F BA /4 ibBT r/m32, imm8BValidValidStore selected bit in CF flag.REX.W + 0F BA/4 ibBT r/m64, imm8BValidN.E.Store selected bit in CF flag.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r)ModRM:reg (r)NANABModRM:r/m (r)imm8NANADescriptionSelects the bit in a bit string (specified with the first operand, called the bit base) atthe bit-position designated by the bit offset (specified by the second operand) andstores the value of the bit in the CF flag.
The bit base operand can be a register or amemory location; the bit offset operand can be a register or an immediate value:•If the bit base operand specifies a register, the instruction takes the modulo 16,32, or 64 of the bit offset operand (modulo size depends on the mode andregister size; 64-bit operands are available only in 64-bit mode).•If the bit base operand specifies a memory location, the operand represents theaddress of the byte in memory that contains the bit base (bit 0 of the specifiedbyte) of the bit string. The range of the bit position that can be referenced by theoffset operand depends on the operand size.See also: Bit(BitBase, BitOffset) on page 3-11.Some assemblers support immediate bit offsets larger than 31 by using the immediate bit offset field in combination with the displacement field of the memoryoperand. In this case, the low-order 3 or 5 bits (3 for 16-bit operands, 5 for 32-bitoperands) of the immediate bit offset are stored in the immediate bit offset field, andthe high-order bits are shifted and combined with the byte displacement in theaddressing mode by the assembler.
The processor will ignore the high order bits ifthey are not zero.When accessing a bit in memory, the processor may access 4 bytes starting from thememory address for a 32-bit operand size, using by the following relationship:3-108 Vol. 2ABT—Bit TestINSTRUCTION SET REFERENCE, A-MEffective Address + (4 ∗ (BitOffset DIV 32))Or, it may access 2 bytes starting from the memory address for a 16-bit operand,using this relationship:Effective Address + (2 ∗ (BitOffset DIV 16))It may do so even when only a single byte needs to be accessed to reach the givenbit. When using this bit addressing mechanism, software should avoid referencingareas of memory close to address space holes. In particular, it should avoid references to memory-mapped I/O registers. Instead, software should use the MOVinstructions to load from or store to these addresses, and use the register form ofthese instructions to manipulate the data.In 64-bit mode, the instruction’s default operation size is 32 bits.
Using a REX prefixin the form of REX.R permits access to additional registers (R8-R15). Using a REXprefix in the form of REX.W promotes operation to 64 bit operands. See the summarychart at the beginning of this section for encoding data and limits.OperationCF ← Bit(BitBase, BitOffset);Flags AffectedThe CF flag contains the value of the selected bit.
The ZF flag is unaffected. The OF,SF, AF, and PF flags are undefined.Protected Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.If the DS, ES, FS, or GS register contains a NULL segmentselector.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.Real-Address Mode Exceptions#GPIf a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SSIf a memory operand effective address is outside the SSsegment limit.#UDIf the LOCK prefix is used.BT—Bit TestVol.
2A 3-109INSTRUCTION SET REFERENCE, A-MVirtual-8086 Mode Exceptions#GP(0)If a memory operand effective address is outside the CS, DS,ES, FS, or GS segment limit.#SS(0)If a memory operand effective address is outside the SSsegment limit.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made.#UDIf the LOCK prefix is used.Compatibility Mode ExceptionsSame exceptions as in protected mode.64-Bit Mode Exceptions#SS(0)If a memory address referencing the SS segment is in a noncanonical form.#GP(0)If the memory address is in a non-canonical form.#PF(fault-code)If a page fault occurs.#AC(0)If alignment checking is enabled and an unaligned memoryreference is made while the current privilege level is 3.#UDIf the LOCK prefix is used.3-110 Vol.
2ABT—Bit TestINSTRUCTION SET REFERENCE, A-MBTC—Bit Test and ComplementOpcodeInstructionOp/En64-bitModeCompat/ DescriptionLeg Mode0F BBBTC r/m16, r16AValidValidStore selected bit in CF flagand complement.0F BBBTC r/m32, r32AValidValidStore selected bit in CF flagand complement.REX.W + 0F BBBTC r/m64, r64AValidN.E.Store selected bit in CF flagand complement.0F BA /7 ibBTC r/m16, imm8BValidValidStore selected bit in CF flagand complement.0F BA /7 ibBTC r/m32, imm8BValidValidStore selected bit in CF flagand complement.REX.W + 0F BA/7 ibBTC r/m64, imm8BValidN.E.Store selected bit in CF flagand complement.Instruction Operand EncodingOp/EnOperand 1Operand 2Operand 3Operand 4AModRM:r/m (r, w)ModRM:reg (r)NANABModRM:r/m (r, w)imm8NANADescriptionSelects the bit in a bit string (specified with the first operand, called the bit base) atthe bit-position designated by the bit offset operand (second operand), stores thevalue of the bit in the CF flag, and complements the selected bit in the bit string.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
