Volume 2A Instruction Set Reference A-M (794101), страница 15
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The default segment register is SS for the effective addresses containing a BP index, DS for othereffective addresses.2. The disp16 nomenclature denotes a 16-bit displacement that follows the ModR/M byte and that isadded to the index.3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte and that issign-extended and added to the index.2-6 Vol. 2AINSTRUCTION FORMATTable 2-2. 32-Bit Addressing Forms with the ModR/M ByteALAXEAXMM0XMM00000r8(/r)r16(/r)r32(/r)mm(/r)xmm(/r)(In decimal) /digit (Opcode)(In binary) REG =Effective AddressModR/MCLCXECXMM1XMM11001DLDXEDXMM2XMM22010BLBXEBXMM3XMM33011AHSPESPMM4XMM44100CHBPEBPMM5XMM55101DHSIESIMM6XMM66110BHDIEDIMM7XMM77111Value of ModR/M Byte (in Hexadecimal)[EAX][ECX][EDX][EBX][--][--]1disp322[ESI][EDI]00000001010011100101110111000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F[EAX]+disp83[ECX]+disp8[EDX]+disp8[EBX]+disp8[--][--]+disp8[EBP]+disp8[ESI]+disp8[EDI]+disp801000001010011100101110111404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F[EAX]+disp32[ECX]+disp32[EDX]+disp32[EBX]+disp32[--][--]+disp32[EBP]+disp32[ESI]+disp32[EDI]+disp3210000001010011100101110111808182838485868788898A8B8C8D8E8F909192939495969798999A9B9C9D9E9FA0A1A2A3A4A5A6A7A8A9AAABACADAEAFB0B1B2B3B4B5B6B7B8B9BABBBCBDBEBFEAX/AX/AL/MM0/XMM0 11ECX/CX/CL/MM/XMM1EDX/DX/DL/MM2/XMM2EBX/BX/BL/MM3/XMM3ESP/SP/AH/MM4/XMM4EBP/BP/CH/MM5/XMM5ESI/SI/DH/MM6/XMM6EDI/DI/BH/MM7/XMM7000001010011100101110111C0C1C2C3C4C5C6C7C8C9CACBCCCDCECFD0D1D2D3D4D5D6D7D8D9DADBDCDDDEDFE0E1E2E3E4E5E6E7E8E9EAEBECEDEEEFF0F1F2F3F4F5F6F7F8F9FAFBFCFDFEFFNOTES:1.
The [--][--] nomenclature means a SIB follows the ModR/M byte.2. The disp32 nomenclature denotes a 32-bit displacement that follows the ModR/M byte (or the SIBbyte if one is present) and that is added to the index.3. The disp8 nomenclature denotes an 8-bit displacement that follows the ModR/M byte (or the SIBbyte if one is present) and that is sign-extended and added to the index.Table 2-3 is organized to give 256 possible values of the SIB byte (in hexadecimal).General purpose registers used as a base are indicated across the top of the table,along with corresponding values for the SIB byte’s base field.
Table rows in the bodyVol. 2A 2-7INSTRUCTION FORMATof the table indicate the register used as the index (SIB byte bits 3, 4 and 5) and thescaling factor (determined by SIB byte bits 6 and 7).Table 2-3. 32-Bit Addressing Forms with the SIB Byter32(In decimal) Base =(In binary) Base =Scaled IndexEAX0000SSECX1001IndexEDX2010EBX3011ESP4100[*]5101ESI6110EDI7111Value of SIB Byte (in Hexadecimal)[EAX][ECX][EDX][EBX]none[EBP][ESI][EDI]0000000101001110010111011100081018202830380109111921293139020A121A222A323A030B131B232B333B040C141C242C343C050D151D252D353D060E161E262E363E070F171F272F373F[EAX*2][ECX*2][EDX*2][EBX*2]none[EBP*2][ESI*2][EDI*2]0100000101001110010111011140485058606870784149515961697179424A525A626A727A434B535B636B737B444C545C646C747C454D555D656D757D464E565E666E767E474F575F676F777F[EAX*4][ECX*4][EDX*4][EBX*4]none[EBP*4][ESI*4][EDI*4]1000000101001110010111011180889098A0A8B0B881899189A1A9B1B9828A929AA2AAB2BA838B939BA3ABB3BB848C949CA4ACB4BC858D959DA5ADB5BD868E969EA6AEB6BE878F979FA7AFB7BF[EAX*8][ECX*8][EDX*8][EBX*8]none[EBP*8][ESI*8][EDI*8]11000001010011100101110111C0C8D0D8E0E8F0F8C1C9D1D9E1E9F1F9C2CAD2DAE2EAF2FAC3CBD3DBE3EBF3FBC4CCD4DCE4ECF4FCC5CDD5DDE5EDF5FDC6CED6DEE6EEF6FEC7CFD7DFE7EFF7FFNOTES:1.
The [*] nomenclature means a disp32 with no base if the MOD is 00B. Otherwise, [*] means disp8or disp32 + [EBP]. This provides the following address modes:MOD bits Effective Address00[scaled index] + disp3201[scaled index] + disp8 + [EBP]10[scaled index] + disp32 + [EBP]2-8 Vol. 2AINSTRUCTION FORMAT2.2IA-32E MODEIA-32e mode has two sub-modes. These are:•Compatibility Mode. Enables a 64-bit operating system to run most legacyprotected mode software unmodified.•64-Bit Mode. Enables a 64-bit operating system to run applications written toaccess 64-bit address space.2.2.1REX PrefixesREX prefixes are instruction-prefix bytes used in 64-bit mode. They do the following:•••Specify GPRs and SSE registers.Specify 64-bit operand size.Specify extended control registers.Not all instructions require a REX prefix in 64-bit mode.
A prefix is necessary only ifan instruction references one of the extended registers or uses a 64-bit operand. If aREX prefix is used when it has no meaning, it is ignored.Only one REX prefix is allowed per instruction. If used, the REX prefix byte mustimmediately precede the opcode byte or the escape opcode byte (0FH). When a REXprefix is used in conjunction with an instruction containing a mandatory prefix, themandatory prefix must come before the REX so the REX prefix can be immediatelypreceding the opcode or the escape byte. For example, CVTDQ2PD with a REX prefixshould have REX placed between F3 and 0F E6.
Other placements are ignored. Theinstruction-size limit of 15 bytes still applies to instructions with a REX prefix. SeeFigure 2-3.LegacyPrefixesREXPrefixGrp 1, Grp2, Grp 3,Grp 4(optional)(optional)OpcodeModR/M1-, 2-, or3-byteopcode1 byte(if required)SIB1 byte(if required)DisplacementAddressdisplacement of1, 2, or 4 bytesImmediateImmediate dataof 1, 2, or 4bytes or noneFigure 2-3. Prefix Ordering in 64-bit ModeVol. 2A 2-9INSTRUCTION FORMAT2.2.1.1EncodingIntel 64 and IA-32 instruction formats specify up to three registers by using 3-bitfields in the encoding, depending on the format:••ModR/M: the reg and r/m fields of the ModR/M byte•Instructions without ModR/M: the reg field of the opcodeModR/M with SIB: the reg field of the ModR/M byte, the base and index fields ofthe SIB (scale, index, base) byteIn 64-bit mode, these formats do not change.
Bits needed to define fields in the64-bit context are provided by the addition of REX prefixes.2.2.1.2More on REX Prefix FieldsREX prefixes are a set of 16 opcodes that span one row of the opcode map andoccupy entries 40H to 4FH. These opcodes represent valid instructions (INC or DEC)in IA-32 operating modes and in compatibility mode. In 64-bit mode, the sameopcodes represent the instruction prefix REX and are not treated as individualinstructions.The single-byte-opcode form of INC/DEC instruction not available in 64-bit mode.INC/DEC functionality is still available using ModR/M forms of the same instructions(opcodes FF/0 and FF/1).See Table 2-4 for a summary of the REX prefix format.
Figure 2-4 though Figure 2-7show examples of REX prefix fields in use. Some combinations of REX prefix fields areinvalid. In such cases, the prefix is ignored. Some additional information follows:•Setting REX.W can be used to determine the operand size but does not solelydetermine operand width. Like the 66H size prefix, 64-bit operand size overridehas no effect on byte-specific operations.•For non-byte operations: if a 66H prefix is used with prefix (REX.W = 1), 66H isignored.••If a 66H override is used with REX and REX.W = 0, the operand size is 16 bits.••REX.X bit modifies the SIB index field.REX.R modifies the ModR/M reg field when that field encodes a GPR, SSE, controlor debug register.
REX.R is ignored when ModR/M specifies other registers ordefines an extended opcode.REX.B either modifies the base in the ModR/M r/m field or SIB base field; or itmodifies the opcode reg field used for accessing GPRs.2-10 Vol. 2AINSTRUCTION FORMATTable 2-4. REX Prefix Fields [BITS: 0100WRXB]Field NameBit PositionDefinition-7:40100W30 = Operand size determined by CS.D1 = 64 Bit Operand SizeR2Extension of the ModR/M reg fieldX1Extension of the SIB index fieldB0Extension of the ModR/M r/m field, SIB base field, orOpcode reg field0RG50%\WH5(;35(),;2SFRGHPRG:5%UHJUUUUPEEE5UUU%EEE20;ILJFigure 2-4. Memory Addressing Without an SIB Byte; REX.X Not Used0RG50%\WH5(;35(),;:5%2SFRGHPRGUHJUUU5UUUUPEEE%EEE20;ILJFigure 2-5.
Register-Register Addressing (No Memory Operand); REX.X Not UsedVol. 2A 2-11INSTRUCTION FORMAT0RG50%\WH5(;35(),;2SFRGH:5;%PRGUHJUUU6,%%\WHUPLQGH[[[[VFDOHVV5UUU;[[[EDVHEEE%EEE20;ILJFigure 2-6. Memory Addressing With a SIB Byte5(;35(),;:%2SFRGHUHJEEE%EEE20;ILJFigure 2-7. Register Operand Coded in Opcode Byte; REX.X & REX.R Not UsedIn the IA-32 architecture, byte registers (AH, AL, BH, BL, CH, CL, DH, and DL) areencoded in the ModR/M byte’s reg field, the r/m field or the opcode reg field as registers 0 through 7.
REX prefixes provide an additional addressing capability for byteregisters that makes the least-significant byte of GPRs available for byte operations.Certain combinations of the fields of the ModR/M byte and the SIB byte have specialmeaning for register encodings. For some combinations, fields expanded by the REXprefix are not decoded.
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