Volume 2A Instruction Set Reference A-M (794101), страница 14
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Intel 64 and IA-32 Architectures Instruction Format2.1.1Instruction PrefixesInstruction prefixes are divided into four groups, each with a set of allowable prefixcodes. For each instruction, it is only useful to include up to one prefix code fromeach of the four groups (Groups 1, 2, 3, 4). Groups 1 through 4 may be placed in anyorder relative to each other.•Group 1— Lock and repeat prefixes:Vol. 2A 2-1INSTRUCTION FORMAT••••LOCK prefix is encoded using F0HREPNE/REPNZ prefix is encoded using F2H. Repeat-Not-Zero prefixapplies only to string and input/output instructions. (F2H is also used as amandatory prefix for some instructions)REP or REPE/REPZ is encoded using F3H. Repeat prefix applies only tostring and input/output instructions.(F3H is also used as a mandatoryprefix for some instructions)Group 2— Segment override prefixes:••2EH—CS segment override (use with any branch instruction is reserved)36H—SS segment override prefix (use with any branch instruction isreserved)•3EH—DS segment override prefix (use with any branch instruction isreserved)•26H—ES segment override prefix (use with any branch instruction isreserved)•64H—FS segment override prefix (use with any branch instruction isreserved)•65H—GS segment override prefix (use with any branch instruction isreserved)— Branch hints:•••3EH—Branch taken (used only with Jcc instructions)Group 3••2EH—Branch not taken (used only with Jcc instructions)Operand-size override prefix is encoded using 66H (66H is also used as amandatory prefix for some instructions).Group 4•67H—Address-size override prefixThe LOCK prefix (F0H) forces an operation that ensures exclusive use of sharedmemory in a multiprocessor environment.
See “LOCK—Assert LOCK# Signal Prefix”in Chapter 3, “Instruction Set Reference, A-M,” for a description of this prefix.Repeat prefixes (F2H, F3H) cause an instruction to be repeated for each element of astring. Use these prefixes only with string and I/O instructions (MOVS, CMPS, SCAS,LODS, STOS, INS, and OUTS). Use of repeat prefixes and/or undefined opcodes withother Intel 64 or IA-32 instructions is reserved; such use may cause unpredictablebehavior.Some instructions may use F2H,F3H as a mandatory prefix to express distinct functionality. A mandatory prefix generally should be placed after other optional prefixes(exception to this is discussed in Section 2.2.1, “REX Prefixes”)2-2 Vol.
2AINSTRUCTION FORMATBranch hint prefixes (2EH, 3EH) allow a program to give a hint to the processor aboutthe most likely code path for a branch. Use these prefixes only with conditionalbranch instructions (Jcc). Other use of branch hint prefixes and/or other undefinedopcodes with Intel 64 or IA-32 instructions is reserved; such use may cause unpredictable behavior.The operand-size override prefix allows a program to switch between 16- and 32-bitoperand sizes. Either size can be the default; use of the prefix selects the non-defaultsize.Some SSE2/SSE3/SSSE3/SSE4 instructions and instructions using a three-bytesequence of primary opcode bytes may use 66H as a mandatory prefix to expressdistinct functionality. A mandatory prefix generally should be placed after otheroptional prefixes (exception to this is discussed in Section 2.2.1, “REX Prefixes”)Other use of the 66H prefix is reserved; such use may cause unpredictable behavior.The address-size override prefix (67H) allows programs to switch between 16- and32-bit addressing.
Either size can be the default; the prefix selects the non-defaultsize. Using this prefix and/or other undefined opcodes when operands for the instruction do not reside in memory is reserved; such use may cause unpredictablebehavior.2.1.2OpcodesA primary opcode can be 1, 2, or 3 bytes in length. An additional 3-bit opcode field issometimes encoded in the ModR/M byte. Smaller fields can be defined within theprimary opcode. Such fields define the direction of operation, size of displacements,register encoding, condition codes, or sign extension.
Encoding fields used by anopcode vary depending on the class of operation.Two-byte opcode formats for general-purpose and SIMD instructions consist of:••An escape opcode byte 0FH as the primary opcode and a second opcode byte, orA mandatory prefix (66H, F2H, or F3H), an escape opcode byte, and a secondopcode byte (same as previous bullet)For example, CVTDQ2PD consists of the following sequence: F3 0F E6.
The first byteis a mandatory prefix (it is not considered as a repeat prefix).Three-byte opcode formats for general-purpose and SIMD instructions consist of:•An escape opcode byte 0FH as the primary opcode, plus two additional opcodebytes, or•A mandatory prefix (66H, F2H, or F3H), an escape opcode byte, plus twoadditional opcode bytes (same as previous bullet)For example, PHADDW for XMM registers consists of the following sequence: 66 0F38 01. The first byte is the mandatory prefix.Valid opcode expressions are defined in Appendix A and Appendix B.Vol. 2A 2-3INSTRUCTION FORMAT2.1.3ModR/M and SIB BytesMany instructions that refer to an operand in memory have an addressing-form specifier byte (called the ModR/M byte) following the primary opcode.
The ModR/M bytecontains three fields of information:•The mod field combines with the r/m field to form 32 possible values: eightregisters and 24 addressing modes.•The reg/opcode field specifies either a register number or three more bits ofopcode information. The purpose of the reg/opcode field is specified in theprimary opcode.•The r/m field can specify a register as an operand or it can be combined with themod field to encode an addressing mode. Sometimes, certain combinations ofthe mod field and the r/m field is used to express opcode information for someinstructions.Certain encodings of the ModR/M byte require a second addressing byte (the SIBbyte).
The base-plus-index and scale-plus-index forms of 32-bit addressing requirethe SIB byte. The SIB byte includes the following fields:•••The scale field specifies the scale factor.The index field specifies the register number of the index register.The base field specifies the register number of the base register.See Section 2.1.5 for the encodings of the ModR/M and SIB bytes.2.1.4Displacement and Immediate BytesSome addressing forms include a displacement immediately following the ModR/Mbyte (or the SIB byte if one is present). If a displacement is required; it be 1, 2, or 4bytes.If an instruction specifies an immediate operand, the operand always follows anydisplacement bytes.
An immediate operand can be 1, 2 or 4 bytes.2.1.5Addressing-Mode Encoding of ModR/M and SIB BytesThe values and corresponding addressing forms of the ModR/M and SIB bytes areshown in Table 2-1 through Table 2-3: 16-bit addressing forms specified by theModR/M byte are in Table 2-1 and 32-bit addressing forms are in Table 2-2. Table 2-3shows 32-bit addressing forms specified by the SIB byte.
In cases where thereg/opcode field in the ModR/M byte represents an extended opcode, valid encodingsare shown in Appendix B.In Table 2-1 and Table 2-2, the Effective Address column lists 32 effective addressesthat can be assigned to the first operand of an instruction by using the Mod and R/Mfields of the ModR/M byte. The first 24 options provide ways of specifying a memory2-4 Vol. 2AINSTRUCTION FORMATlocation; the last eight (Mod = 11B) provide ways of specifying general-purpose,MMX technology and XMM registers.The Mod and R/M columns in Table 2-1 and Table 2-2 give the binary encodings of theMod and R/M fields required to obtain the effective address listed in the first column.For example: see the row indicated by Mod = 11B, R/M = 000B.
The row identifiesthe general-purpose registers EAX, AX or AL; MMX technology register MM0; or XMMregister XMM0. The register used is determined by the opcode byte and the operandsize attribute.Now look at the seventh row in either table (labeled “REG =”). This row specifies theuse of the 3-bit Reg/Opcode field when the field is used to give the location of asecond operand. The second operand must be a general-purpose, MMX technology,or XMM register.
Rows one through five list the registers that may correspond to thevalue in the table. Again, the register used is determined by the opcode byte alongwith the operand-size attribute.If the instruction does not require a second operand, then the Reg/Opcode field maybe used as an opcode extension. This use is represented by the sixth row in thetables (labeled “/digit (Opcode)”). Note that values in row six are represented indecimal form.The body of Table 2-1 and Table 2-2 (under the label “Value of ModR/M Byte (in Hexadecimal)”) contains a 32 by 8 array that presents all of 256 values of the ModR/Mbyte (in hexadecimal).
Bits 3, 4 and 5 are specified by the column of the table inwhich a byte resides. The row specifies bits 0, 1 and 2; and bits 6 and 7. The figurebelow demonstrates interpretation of one table value.Mod 11RM000/digit (Opcode); REG =001C8H 11001000Figure 2-2. Table Interpretation of ModR/M Byte (C8H)Vol. 2A 2-5INSTRUCTION FORMATTable 2-1. 16-Bit Addressing Forms with the ModR/M ByteALAXEAXMM0XMM00000r8(/r)r16(/r)r32(/r)mm(/r)xmm(/r)(In decimal) /digit (Opcode)(In binary) REG =Effective AddressCLCXECXMM1XMM11001DLDXEDXMM2XMM22010BLBXEBXMM3XMM33011AHSPESPMM4XMM44100CHBP1EBPMM5XMM55101DHSIESIMM6XMM66110BHDIEDIMM7XMM77111ModR/M[BX+SI][BX+DI][BP+SI][BP+DI][SI][DI]disp162[BX]000000010100111001011101110001020304050607Value of ModR/M Byte (in Hexadecimal)08090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F202122232425262728292A2B2C2D2E2F303132333435363738393A3B3C3D3E3F[BX+SI]+disp83[BX+DI]+disp8[BP+SI]+disp8[BP+DI]+disp8[SI]+disp8[DI]+disp8[BP]+disp8[BX]+disp801000001010011100101110111404142434445464748494A4B4C4D4E4F505152535455565758595A5B5C5D5E5F606162636465666768696A6B6C6D6E6F707172737475767778797A7B7C7D7E7F[BX+SI]+disp16[BX+DI]+disp16[BP+SI]+disp16[BP+DI]+disp16[SI]+disp16[DI]+disp16[BP]+disp16[BX]+disp1610000001010011100101110111808182838485868788898A8B8C8D8E8F909192939495969798999A9B9C9D9E9FA0A1A2A3A4A5A6A7A8A9AAABACADAEAFB0B1B2B3B4B5B6B7B8B9BABBBCBDBEBFEAX/AX/AL/MM0/XMM0 11ECX/CX/CL/MM1/XMM1EDX/DX/DL/MM2/XMM2EBX/BX/BL/MM3/XMM3ESP/SP/AHMM4/XMM4EBP/BP/CH/MM5/XMM5ESI/SI/DH/MM6/XMM6EDI/DI/BH/MM7/XMM7000001010011100101110111C0C1C2C3C4C5C6C7C8C9CACBCCCDCECFD0D1D2D3D4D5D6D7D8D9DADBDCDDDEDFE0EQE2E3E4E5E6E7E8E9EAEBECEDEEEFF0F1F2F3F4F5F6F7F8F9FAFBFCFDFEFFNOTES:1.
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