Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 30
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3.08—July 2007PUNPCKHDQUnpack and Interleave High DoublewordsUnpacks the high-order doublewords from the first and second source operands and packs them intointerleaved-doubleword quadwords in the destination (first source). The low-order doublewords of thesource operands are ignored. The first source/destination operand is an MMX register and the secondsource operand is another MMX register or 64-bit memory location.If the second source operand is all 0s, the destination contains the doubleword(s) from the first sourceoperand zero-extended to 64 bits. This operation is useful for expanding unsigned 32-bit values tounsigned 64-bit operands for subsequent processing that requires higher precision.The PUNPCKHDQ instruction is an MMX™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKHDQ mmx1,mmx2/mem64Description0F 6A /rUnpacks the high-order doubleword in an MMX registerand another MMX register or 64-bit memory locationand packs them into interleaved doublewords in thedestination MMX register.mmx16332 31mmx2/mem64063copy32 310copy6332 310punpckhdq-64.epsRelated InstructionsP U N P C K H B W, P U N P C K H Q D Q , P U N P C K H W D , P U N P C K L B W, P U N P C K L D Q ,PUNPCKLQDQ, PUNPCKLWDrFLAGS AffectedNone204PUNPCKHDQInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPUNPCKHDQ205AMD64 Technology26569—Rev.
3.08—July 2007PUNPCKHWDUnpack and Interleave High WordsUnpacks the high-order words from the first and second source operands and packs them intointerleaved-word doublewords in the destination (first source). The low-order words of the sourceoperands are ignored. The first source/destination operand is an MMX register and the second sourceoperand is another MMX register or 64-bit memory location.If the second source operand is all 0s, the destination contains the words from the first source operandzero-extended to 32 bits. This operation is useful for expanding unsigned 16-bit values to unsigned 32bit operands for subsequent processing that requires higher precision.The PUNPCKHWD instruction is an MMX™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKHWD mmx1,mmx2/mem640F 69 /rDescriptionUnpacks two high-order words in an MMX registerand another MMX register or 64-bit memorylocation and packs them into interleaved words inthe destination MMX register.mmx16348 47 32 31copymmx2/mem64630copycopy63 48 47 32 31 16 15048 47 32 310copypunpckhwd-64.epsRelated InstructionsPUNPCKHBW, PUNPCKHDQ, PUNPCKHQDQ, PUNPCKLBW, PUNPCKLDQ, PUNPCKLQDQ,PUNPCKLWDrFLAGS AffectedNone206PUNPCKHWDInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPUNPCKHWD207AMD64 Technology26569—Rev.
3.08—July 2007PUNPCKLBWUnpack and Interleave Low BytesUnpacks the low-order bytes from the first and second source operands and packs them intointerleaved-byte words in the destination (first source). The high-order bytes of the source operandsare ignored. The first source/destination operand is an MMX register and the second source operand isanother MMX register or 32-bit memory location.If the second source operand is all 0s, the destination contains the bytes from the first source operandzero-extended to 16 bits. This operation is useful for expanding unsigned 8-bit values to unsigned 16bit operands for subsequent processing that requires higher precision.The PUNPCKLBW instruction is an MMX™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKLBW mmx1, mmx2/mem32DescriptionUnpacks the four low-order bytes in an MMXregister and another MMX register or 32-bitmemory location and packs them into interleavedbytes in the destination MMX register.0F 60 /rmmx163mmx2/mem6432 310.copy6332 31.0.copycopy.63. ..copy.32 310punpcklbw-64.epsRelated InstructionsP U N P C K H B W, P U N P C K H D Q , P U N P C K H Q D Q , P U N P C K H W D , P U N P C K L D Q ,PUNPCKLQDQ, PUNPCKLWDrFLAGS AffectedNone208PUNPCKLBWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPUNPCKLBW209AMD64 Technology26569—Rev.
3.08—July 2007PUNPCKLDQUnpack and Interleave Low DoublewordsUnpacks the low-order doublewords from the first and second source operands and packs them intointerleaved-doubleword quadwords in the destination (first source). The high-order doublewords ofthe source operands are ignored. The first source/destination operand is an MMX register and thesecond source operand is another MMX register or 32-bit memory location.If the second source operand is all 0s, the destination contains the doubleword(s) from the first sourceoperand zero-extended to 64 bits. This operation is useful for expanding unsigned 32-bit values tounsigned 64-bit operands for subsequent processing that requires higher precision.The PUNPCKLDQ instruction is an MMX™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKLDQ mmx1,mmx2/mem320F 62 /rDescriptionUnpacks the low-order doubleword in an MMX registerand another MMX register or 32-bit memory locationand packs them into interleaved doublewords in thedestination MMX register.mmx16332 31mmx2/mem64063copy32 310copy6332 310punpckldq-64.epsRelated InstructionsP U N P C K H B W, P U N P C K H D Q , P U N P C K H Q D Q , P U N P C K H W D , P U N P C K L B W,PUNPCKLQDQ, PUNPCKLWDrFLAGS AffectedNone210PUNPCKLDQInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACX64-Bit Media Instruction Reference211AMD64 Technology26569—Rev.
3.08—July 2007PUNPCKLWDUnpack and Interleave Low WordsUnpacks the low-order words from the first and second source operands and packs them intointerleaved-word doublewords in the destination (first source). The high-order words of the sourceoperands are ignored. The first source/destination operand is an MMX register and the second sourceoperand is another MMX register or 32-bit memory location.If the second source operand is all 0s, the destination contains the words from the first source operandzero-extended to 32 bits. This operation is useful for expanding unsigned 16-bit values to unsigned 32bit operands for subsequent processing that requires higher precision.The PUNPCKLWD instruction is an MMX™ instruction. The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKLWD mmx1, mmx2/mem320F 61 /rDescriptionUnpacks the two low-order words in an MMXregister and another MMX register or 32-bitmemory location and packs them into interleavedwords in the destination MMX register.mmx16332 31mmx2/mem6416 15copy630copy32 31copy63 48 47 32 31 16 15016 150copypunpcklwd-64.epsRelated InstructionsPUNPCKHBW, PUNPCKHDQ, PUNPCKHQDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ,PUNPCKLQDQrFLAGS AffectedNone21264-Bit Media Instruction Reference26569—Rev.
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