Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 25
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3.08—July 2007AMD64 TechnologyPMULHWPacked Multiply High Signed WordMultiplies each packed 16-bit signed integer value in the first source operand by the correspondingpacked 16-bit signed integer in the second source operand and writes the high-order 16 bits of theintermediate 32-bit result of each multiplication in the corresponding word of the destination (firstsource). The first source/destination operand is an MMX register and the second source operand isanother MMX register or 64-bit memory location.The PMULHW instruction is an MMX™ instruction. The presence of this instruction set is indicatedby CPUID feature bits.
(See “CPUID” in Volume 3.)MnemonicOpcodePMULHW mmx1, mmx2/mem640F E5 /rDescriptionMultiplies packed 16-bit signed integer values in anMMX register and another MMX register or 64-bitmemory location and writes the high-order 16 bits ofeach result in the destination MMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.multiplymultiplypmulhw-64.epsRelated InstructionsPMADDWD, PMULHUW, PMULLW, PMULUDQrFLAGS AffectedNoneInstruction ReferencePMULHW155AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC156XPMULHWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPMULLWPacked Multiply Low Signed WordMultiplies each packed 16-bit signed integer value in the first source operand by the correspondingpacked 16-bit signed integer in the second source operand and writes the low-order 16 bits of theintermediate 32-bit result of each multiplication in the corresponding word of the destination (firstsource). The first source/destination operand is an MMX register and the second source operand isanother MMX register or 64-bit memory location.The PMULLW instruction is an MMX™ instruction. The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePMULLW mmx1, mmx2/mem640F D5 /rDescriptionMultiplies packed 16-bit signed integer values in anMMX register and another MMX register or 64-bitmemory location and writes the low-order 16 bits ofeach result in the destination MMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.multiplymultiplypmullw-64.epsRelated InstructionsPMADDWD, PMULHUW, PMULHW, PMULUDQrFLAGS AffectedNoneInstruction ReferencePMULLW157AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC158XPMULLWInstruction Reference26569—Rev.
3.08—July 2007PMULUDQAMD64 TechnologyPacked Multiply Unsigned Doubleword and StoreQuadwordMultiplies two 32-bit unsigned integer values in the low-order doubleword of the first and secondsource operands and writes the 64-bit result in the destination (first source). The firstsource/destination operand is an MMX register and the second source operand is another MMXregister or 64-bit memory location.The PMULUDQ instruction is an SSE2 instruction. The presence of this instruction set is indicated byCPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePMULUDQ mmx1, mmx2/mem64DescriptionMultiplies low-order 32-bit unsigned integer value inan MMX register and another MMX register or 64-bitmemory location and writes the 64-bit result in thedestination MMX register.0F F4 /rmmx163mmx2/mem6432 3106332 310multiplypmuludq-64.epsRelated InstructionsPMADDWD, PMULHUW, PMULHW, PMULLWrFLAGS AffectedNoneInstruction ReferencePMULUDQ159AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 in CPUID function0000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC160XPMULUDQInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPORPacked Logical Bitwise ORPerforms a bitwise logical OR of the values in the first and second source operands and writes theresult in the destination (first source). The first source/destination operand is an MMX register and thesecond source operand is another MMX register or 64-bit memory location.The POR instruction is an MMX™ instruction. The presence of this instruction set is indicated byCPUID feature bits.
(See “CPUID” in Volume 3.)MnemonicOpcodePOR mmx1, mmx2/mem64DescriptionPerforms bitwise logical OR of values in an MMX registerand in another MMX register or 64-bit memory location andwrites the result in the destination MMX register.0F EB /rmmx1mmx2/mem64063630ORpor-64.epsRelated InstructionsPAND, PANDN, PXORrFLAGS AffectedNoneInstruction ReferencePOR161AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function 0000_0001hor function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDPage fault, #PFx87 floating-pointexception pending,#MFAlignment check, #AC162XPORInstruction Reference26569—Rev.
3.08—July 2007PSADBWAMD64 TechnologyPacked Sum of Absolute Differences of Bytes Intoa WordComputes the absolute differences of eight corresponding packed 8-bit unsigned integers in the firstand second source operands and writes the unsigned 16-bit integer result of the sum of the eightdifferences in a word in the destination (first source). The first source/destination operand is an MMXregister and the second source operand is another MMX register or 64-bit memory location.
The resultis stored in the low-order word of the destination operand, and the remaining bytes in the destinationare cleared to all 0s.The PSADBW instruction is an AMD extension to MMX™ instruction set and is an SSE instruction.The presence of this instruction set is indicated by CPUID feature bits.
(See “CPUID” in Volume 3.)MnemonicOpcodePSADBW mmx1, mmx2/mem64Description0F F6 /rCompute the sum of the absolute differences ofpacked 8-bit unsigned integer values in an MMXregister and another MMX register or 64-bit memorylocation and writes the 16-bit unsigned integer result inthe destination MMX register.mmx1mmx2/mem64630.....63.0......absolutedifferenceabsolutedifferenceadd 8pairs631500psadbw-64.epsrFLAGS AffectedNoneInstruction ReferencePSADBW163AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to MMX are not supported, asindicated by EDX bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC164XPSADBWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPSHUFWPacked Shuffle WordsMoves any one of the four packed words in an MMX register or 64-bit memory location to a specifiedword location in another MMX register. In each case, the selection of the value of the destination wordis determined by a two-bit field in the immediate-byte operand, with bits 0 and 1 selecting the contentsof the low-order word, bits 2 and 3 selecting the second word, bits 4 and 5 selecting the third word, andbits 6 and 7 selecting the high-order word. Refer to Table 1-20 on page 166.
A word in the sourceoperand may be copied to more than one word in the destination.The PSHUFW instruction is an AMD extension to MMX™ instruction set and is an SSE instruction.The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePSHUFW mmx1, mmx2/mem64,imm8DescriptionShuffles packed 16-bit values in an MMXregister or 64-bit memory location and puts theresult in another XMM register.0F 70 /r ibmmx1mmx2/mem6463 48 47 32 31 16 15063 48 47 32 31 16 150imm87 0muxmuxmuxmuxpshufw.epsInstruction ReferencePSHUFW165AMD64 Technology26569—Rev.
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