Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 24
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(See “CPUID” in Volume 3.)MnemonicOpcodePMINSW mmx1, mmx2/mem640F EA /rDescriptionCompares packed signed 16-bit integer values in anMMX register and another MMX register or 64-bitmemory location and writes the minimum value of eachcompare in the destination MMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.minimumminimumpminsw-64.epsRelated InstructionsPMAXSW, PMAXUB, PMINUBrFLAGS AffectedNoneInstruction ReferencePMINSW145AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to MMX are not supported, asindicated by EDX bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC146XPMINSWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPMINUBPacked Minimum Unsigned BytesCompares each of the packed 8-bit unsigned integer values in the first source operand with thecorresponding packed 8-bit unsigned integer value in the second source operand and writes theminimum of the two values for each comparison in the corresponding byte of the destination (firstsource). The first source/destination operand is an MMX register and the second source operand isanother MMX register or 64-bit memory location.The PMINUB instruction is an AMD extension to MMX™ instruction set and is an SSE instruction.The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePMINUB mmx1, mmx2/mem640F DA /rDescriptionCompares packed unsigned 8-bit integer values in anMMX register and another MMX register or 64-bitmemory location and writes the minimum value of eachcomparison in the destination MMX register.mmx1....mmx2/mem64..630.....63.0......minimumminimumpminub-64.epsRelated InstructionsPMAXSW, PMAXUB, PMINSWrFLAGS AffectedNoneInstruction ReferencePMINUB147AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to MMX are not supported, asindicated by EDX bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC148XPMINUBInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPMOVMSKBPacked Move Mask ByteMoves the most-significant bit of each byte in the source operand in bitwise order to the low order byteof the destination operand. The upper 24 bits of the destination operand are cleared to zeros. Thedestination operand is a 32-bit general-purpose register and the source operand is an MMX register.The PMOVMSKB instruction is an AMD extension to MMX™ instruction set and is an SSEinstruction. The presence of this instruction set is indicated by CPUID feature bits.
(See “CPUID” inVolume 3.)MnemonicOpcodePMOVMSKB reg32, mmxDescriptionMoves most-significant bit of each byte in an MMX registerto the low-order byte of a 32-bit general-purpose register.0F D7 /rreg32mmx......73163 55 47 39 31 23 15 7 000. .. ...copycopypmovmskb-64.epsRelated InstructionsMOVMSKPD, MOVMSKPSrFLAGS AffectedNoneInstruction ReferencePMOVMSKB149AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicated byEDX bit 25 in CPUID function 0000_0001h; and theAMD extensions to MMX are not supported, asindicated by EDX bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.Invalid opcode, #UD150PMOVMSKBInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPMULHRWPacked Multiply High Rounded WordMultiplies each of the four packed 16-bit signed integer values in the first source operand by thecorresponding packed 16-bit integer value in the second source operand, adds 8000h to the lower 16bits of the intermediate 32-bit result of each multiplication, and writes the high-order 16 bits of eachresult in the corresponding word of the destination (first source).
The addition of 8000h results in therounding of the result, providing a numerically more accurate result than the PMULHW instruction,which truncates the result. The first source/destination operand is an MMX register. The second sourceoperand is another MMX register or 64-bit memory location.The PMULHRW instruction is an AMD 3DNow!™ instruction. The presence of this instruction set isindicated by CPUID feature bits.
(See “CPUID” in Volume 3.)MnemonicOpcode0F 0F /rB7PMULHRW mmx1, mmx2/mem64DescriptionMultiply 16-bit signed integer values in an MMX registerand another MMX register or 64-bit memory location andwrite rounded result in the destination MMX register.mmx1.63mmx2/mem64.48 47 32 31 16 15.063.48 47 32 31 16 15.0.multiplyroundmultiplyroundpmulhrw.epsRelated InstructionsNonerFLAGS AffectedNoneInstruction ReferencePMULHRW151AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC152XPMULHRWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPMULHUWPacked Multiply High Unsigned WordMultiplies each packed unsigned 16-bit values in the first source operand by the corresponding packedunsigned word in the second source operand and writes the high-order 16 bits of each intermediate 32bit result in the corresponding word of the destination (first source). The first source/destinationoperand is an MMX register and the second source operand is another MMX register or 64-bit memorylocation.The PMULHUW instruction is an AMD extension to MMX™ instruction set and is an SSEinstruction. The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” inVolume 3.)MnemonicOpcodePMULHUW mmx1, mmx2/mem64DescriptionMultiplies packed 16-bit values in an MMX registerby the packed 16-bit values in another MMX registeror 64-bit memory location and writes the high-order16 bits of each result in the destination MMXregister.0F E4 /rmmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.multiplymultiplypmulhuw-64.epsRelated InstructionsPMADDWD, PMULHW, PMULLW, PMULUDQrFLAGS AffectedNoneInstruction ReferencePMULHUW153AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to MMX are not supported, asindicated by EDX bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC154XPMULHUWInstruction Reference26569—Rev.
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