Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 22
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3.08—July 2007Table 1-17. Numeric Range for the PFSUB ResultsSource 2Source Operand00Source 1 andDestination+/–Normal01Unsupported- Source 2NormalSource 1Normal, +/– 0Unsupported3Source 1Undefined- Source 22UndefinedUndefinedNote:1. The sign of the result is the logical AND of the sign of source 1 and the inverse of the sign of source 2.2.
If the absolute value of the infinitely precise result is less than 2–126 (but not zero), the result is a zero.If the source operand that is larger in magnitude is source 1, the sign of this zero is the same as the signof source 1, else it is the inverse of the sign of source 2. If the infinitely precise result is exactly zero, theresult is zero with the sign of source 1. If the absolute value of the infinitely precise result is greater thanor equal to 2128, the result is the largest normal number with the sign of source 1.3.
“Unsupported” means that the exponent is all ones (1s).Related InstructionsPFSUBRrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC130XPFSUBInstruction Reference26569—Rev.
3.08—July 2007PFSUBRAMD64 TechnologyPacked Floating-Point Subtract ReverseSubtracts each packed single-precision floating-point value in the first source operand from thecorresponding packed single-precision floating-point value in the second source operand and writesthe result of each subtraction in the corresponding dword of the destination (first source). The firstsource/destination operand is an MMX register. The second source operand is another MMX registeror 64-bit memory location. The numeric range for operands is shown in Table 1-18 on page 132.The PFSUBR instruction is an AMD 3DNow!™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionSUBPSMnemonicOpcodePFSUBR mmx1, mmx2/mem640F 0F /rAADescriptionSubtracts packed single-precision floating-point values inan MMX register from packed single-precision floatingpoint values in another MMX register or 64-bit memorylocation and writes the result in the destination MMXregister.mmx16332 31mmx2/mem6406332 310subtractsubtractpfsubr.epsInstruction ReferencePFSUBR131AMD64 Technology26569—Rev.
3.08—July 2007Table 1-18. Numeric Range for the PFSUBR ResultsSource 2Source Operand00Source 1 andDestination+/–Normal01UnsupportedSource 2Normal- Source 1Normal, +/– 0Unsupported3- Source 1UndefinedSource 22UndefinedUndefinedNote:1. The sign is the logical AND of the sign of source 2 and the inverse of the sign of source 1.2. If the absolute value of the infinitely precise result is less than 2–126 (but not zero), the result is a zero.If the source operand that is larger in magnitude is source 2, the sign of this zero is the same as the signof source 2, else it is the inverse of the sign of source 1. If the infinitely precise result is exactly zero, theresult is zero with the sign of source 2.
If the absolute value of the infinitely precise result is greater thanor equal to 2128, the result is the largest normal number with the sign of source 2.3. “Unsupported” means that the exponent is all ones (1s).Related InstructionsPFSUBrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC132XPFSUBRInstruction Reference26569—Rev.
3.08—July 2007PI2FDAMD64 TechnologyPacked Integer to Floating-Point DoublewordConversionConverts two packed 32-bit signed integer values in an MMX register or a 64-bit memory location totwo packed single-precision floating-point values and writes the converted values in another MMXregister. If the result of the conversion is an inexact value, the value is truncated (rounded toward zero).The PI2FD instruction is an AMD 3DNow!™ instruction. The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionCVTDQ2PSMnemonicOpcodePI2FD mmx1,mmx2/mem64DescriptionConverts packed doubleword integers in an MMX register or 64bit memory location to single-precision floating-point values inthe destination MMX register.
Inexact results are truncated.0F 0F /r0Dmmx16332 31mmx2/mem6406332 310convertconvertpi2fd.epsRelated InstructionsPF2ID, PF2IW, PI2FWrFLAGS AffectedNoneInstruction ReferencePI2FD133AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC134XPI2FDInstruction Reference26569—Rev.
3.08—July 2007PI2FWAMD64 TechnologyPacked Integer to Floating-Point Word ConversionConverts two packed 16-bit signed integer values in an MMX register or a 64-bit memory location totwo packed single-precision floating-point values and writes the converted values in another MMXregister.The PI2FW instruction is an extension to the AMD 3DNow!™ instruction set. The presence of thisinstruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePI2FW mmx1,mmx2/mem64DescriptionConverts packed 16-bit integers in an MMX register or 64-bitmemory location to packed single-precision floating-pointvalues in the destination MMX register.0F 0F /r0Cmmx16332 31mmx2/mem6463 48 47 32 31 16 1500convertconvertpi2fw.epsRelated InstructionsPF2ID, PF2IW, PI2FDInstruction ReferencePI2FW135AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD extensions to 3DNow!™ are not supported,as indicated by EDX bit 30 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC136XPI2FWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPINSRWPacked Insert WordInserts a 16-bit value from the low-order word of a 32-bit general purpose register or a 16-bit memorylocation into an MMX register. The location in the destination register is selected by the immediatebyte operand, a shown in Table 1-19. The other words in the destination register operand are notmodified.The PINSRW instruction is an AMD extension to MMX™ instruction set and is an SSE instruction.The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePINSRW mmx, reg32/mem16,imm8DescriptionInserts a 16-bit value from a general-purposeregister or memory location into an MMXregister.0F C4 /r ibmmxreg32/mem1663 48 47 32 31 16 15031015imm87 0select word position for insertpinsrw-64.epsTable 1-19.
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