Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 18
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The result is FFFF_FFFFh, if source 1 is positive. Otherwise, the result is 0000_0000h.3. The result is FFFF_FFFFh, if source 1 is positive and source 2 is negative, or if they are both negativeand source 1 is smaller in magnitude than source 2, or if source 1 and source 2 are positive and source1 is greater in magnitude than source 2. The result is 0000_0000h in all other cases.4. “Unsupported” means that the exponent is all ones (1s).Related InstructionsPFCMPEQ, PFCMPGErFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by bit 31 in CPUID function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPFCMPGT101AMD64 TechnologyPFMAX26569—Rev.
3.08—July 2007Packed Single-Precision Floating-Point MaximumCompares each of the two packed single-precision floating-point values in the first source operandwith the corresponding packed single-precision floating-point value in the second source operand andwrites the maximum of the two values for each comparison in the corresponding doubleword of thedestination (first source). The first source/destination operand is an MMX register.
The second sourceoperand is another MMX register or 64-bit memory location.Any operation with a zero and a negative number returns positive zero. An operation consisting of twozeros returns positive zero. If either source operand is an undefined value, the result is undefined. Thenumeric range for source and destination operands is shown in Table 1-9 on page 103.The PFMAX instruction is an AMD 3DNow!™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionMAXPSMnemonicOpcode0F 0F /rA4PFMAX mmx1, mmx2/mem64DescriptionCompares two pairs of packed single-precision values in anMMX register and another MMX register or 64-bit memorylocation and writes the maximum value of each comparisonin the destination MMX register.mmx16332 31mmx2/mem6406332 310maximummaximumpfmax.eps102PFMAXInstruction Reference26569—Rev.
3.08—July 2007Table 1-9.AMD64 TechnologyNumeric Range for the PFMAX InstructionSource 2OperandValue00Source 1 andDestinationNormal+0Source 2,2Unsupported+01Undefined3NormalSource 1, +0Source 1/Source 2UndefinedUnsupported4UndefinedUndefinedUndefinedNote:1. The result is source 2, if source 2 is positive.
Otherwise, the result is positive zero.2. The result is source 1, if source 1 is positive. Otherwise, the result is positive zero.3. The result is source 1, if source 1 is positive and source 2 is negative. The result is source 1, if both arepositive and source 1 is greater in magnitude than source 2. The result is source 1, if both are negativeand source 1 is lesser in magnitude than source 2. The result is source 2 in all other cases.4.
“Unsupported” means that the exponent is all ones (1s).Related InstructionsPFMINrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPFMAX103AMD64 TechnologyPFMIN26569—Rev.
3.08—July 2007Packed Single-Precision Floating-Point MinimumCompares each of the two packed single-precision floating-point values in the first source operandwith the corresponding packed single-precision floating-point value in the second source operand andwrites the minimum of the two values for each comparison in the corresponding doubleword of thedestination (first source). The first source/destination operand is an MMX register. The second sourceoperand is another MMX register or 64-bit memory location.Any operation with a zero and a positive number returns positive zero. An operation consisting of twozeros returns positive zero. If either source operand is an undefined value, the result is undefined.
Thenumeric range for source and destination operands is shown in Table 1-10 on page 105.The PFMIN instruction is an AMD 3DNow!™ instruction. The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionMINPSMnemonicOpcode0F 0F /r94PFMIN mmx1, mmx2/mem64DescriptionCompares two pairs of packed single-precision values in anMMX register and another MMX register or 64-bit memorylocation and writes the minimum value of each comparison inthe destination MMX register.mmx16332 31mmx2/mem6406332 310minimumminimumpfmin.eps104PFMINInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyTable 1-10. Numeric Range for the PFMIN InstructionSource 2OperandValue00Source 1 andDestinationNormal+0Source 2,2Unsupported+01Undefined3NormalSource 1, +0Source 1/Source 2UndefinedUnsupported4UndefinedUndefinedUndefinedNote:1. The result is source 2, if source 2 is negative. Otherwise, the result is positive zero.2. The result is source 1, if source 1 is negative. Otherwise, the result is positive zero.3.
The result is source 1, if source 1 is negative and source 2 is positive. The result is source 1, if both arenegative and source 1 is greater in magnitude than source 2. The result is source 1, if both are positiveand source 1 is lesser in magnitude than source 2. The result is source 2 in all other cases.4. “Unsupported” means that the exponent is all ones (1s).Related InstructionsPFMAXrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPFMIN105AMD64 Technology26569—Rev.
3.08—July 2007PFMULPacked Floating-Point MultiplyMultiplies each of the two packed single-precision floating-point values in the first source operand bythe corresponding packed single-precision floating-point value in the second source operand andwrites the result of each multiplication in the corresponding doubleword of the destination (firstsource). The numeric range for source and destination operands is shown in Table 1-11 on page 107.The first source/destination operand is an MMX register.
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