Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 16
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If the result of the conversion is an inexact value, the value is truncated (rounded toward zero).The numeric range for source and destination operands is shown in Table 1-2.The PF2ID instruction is an AMD 3DNow!™ instruction. The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionCVTTPS2DQMnemonicOpcodePF2ID mmx1,mmx2/mem64DescriptionConverts packed single-precision floating-point values in anMMX register or memory location to a doubleword integer valuein the destination MMX register.0F 0F /r1Dmmx16332 31mmx2/mem6406332 310convertconvertpf2id.epsTable 1-2.Numeric Range for PF2ID ResultsSource 2Source 1 and Destination00Normal, abs(Source 2) < 10Normal, –231 < Source 2 <= –1Round to zero (Source 2)Normal, 1 <= Source 2 < 231Round to zero (Source 2)86PF2IDInstruction Reference26569—Rev.
3.08—July 2007Table 1-2.AMD64 TechnologyNumeric Range for PF2ID ResultsSource 2Source 1 and DestinationNormal, Source 2 >= 2317FFF_FFFFhNormal, Source 2 <= –2318000_0000hUnsupportedUndefinedRelated InstructionsPF2IW, PI2FD, PI2FWrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPF2ID87AMD64 TechnologyPF2IW26569—Rev.
3.08—July 2007Packed Floating-Point to Integer Word ConversionConverts two packed single-precision floating-point values in an MMX register or a 64-bit memorylocation to two packed 16-bit signed integer values, sign-extended to 32 bits, and writes the convertedvalues in another MMX register. If the result of the conversion is an inexact value, the value istruncated (rounded toward zero). The numeric range for source and destination operands is shown inTable 1-3 on page 88.
Arguments outside the range representable by signed 16-bit integers aresaturated to the largest and smallest 16-bit integer, depending on their sign.The PF2IW instruction is an extension to the AMD 3DNow!™ instruction set. The presence of thisinstruction set is indicated by CPUID feature bits.
(See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionCVTTPS2DQMnemonicOpcodePF2IW mmx1,mmx2/mem64DescriptionConverts packed single-precision floating-point values in anMMX register or memory location to word integer values in thedestination MMX register.0F 0F /r1Cmmx16332 31smmx2/mem6406332 310sconvertconvertpf2iw.epsTable 1-3.Numeric Range for PF2IW ResultsSource 2Source 1 and Destination00Normal, abs(Source 2) < 1Normal,–215 <0Source 2 <= –115Normal, 1 <= Source 2 < 288Round to zero (Source 2)Round to zero (Source 2)PF2IWInstruction Reference26569—Rev.
3.08—July 2007Table 1-3.AMD64 TechnologyNumeric Range for PF2IW ResultsSource 2Source 1 and DestinationNormal, Source 2 >= 2150000_7FFFhNormal, Source 2 <= –215FFFF_8000hUnsupportedUndefinedRelated InstructionsPF2ID, PI2FD, PI2FWrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD extensions to 3DNow!™ are not supported,as indicated by EDX bit 30 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPF2IW89AMD64 Technology26569—Rev.
3.08—July 2007PFACCPacked Floating-Point AccumulateAdds the two single-precision floating-point values in the first source operand and adds the two singleprecision values in the second source operand and writes the two results to the low-order and highorder doubleword, respectively, of the destination (first source).
The first source/destination operand isan MMX register. The second source operand is another MMX register or 64-bit memory location.The PFACC instruction is an AMD 3DNow!™ instruction. The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionHADDPSMnemonicOpcodePFACC mmx1, mmx2/mem640F 0F /rAEDescriptionAccumulates packed single-precision floating-point values inan MMX register or 64-bit memory location and another MMXregister and writes each result in the destination MMXregister.mmx16332 31mmx2/mem64063add32 310addpfacc.epsThe numeric range for operands is shown in Table 1-4 on page 91.90PFACCInstruction Reference26569—Rev.
3.08—July 2007Table 1-4.AMD64 TechnologyNumeric Range for PFACC ResultsHigh Operand2Source Operand00Low Operand1+/– 0Normal3NormalLow OperandUnsupported5Low OperandUnsupportedHigh OperandNormal, +/–High Operand04UndefinedUndefinedUndefinedNote:1.2.3.4.Least-significant floating-point value in first or second source operand.Most-significant floating-point value in first or second source operand.The sign of the result is the logical AND of the signs of the low and high operands.If the absolute value of the infinitely precise result is less than 2–126 (but not zero), the result is a zerowith the sign of the operand (low or high) that is larger in magnitude.
If the infinitely precise result isexactly zero, the result is zero with the sign of the low operand. If the absolute value of the infinitelyprecise result is greater than or equal to 2128, the result is the largest normal number with the sign ofthe low operand.5. “Unsupported” means that the exponent is all ones (1s).Related InstructionsPFADD, PFNACC, PFPNACCrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPFACC91AMD64 Technology26569—Rev.
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