Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 14
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(See “CPUID” in Volume3.)MnemonicOpcodePAVGB mmx1, mmx2/mem640F E0 /rDescriptionAverages packed 8-bit unsigned integer values in anMMX register and another MMX register or 64-bitmemory location and writes the result in thedestination MMX register.mmx1....mmx2/mem64..630.....63.0......averageaveragepavgb-64.epsRelated InstructionsPAVGWrFLAGS AffectedNone66PAVGBInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby bit 25 in CPUID function 0000_0001h; and theAMD extensions to the MMX™ instruction set are notsupported, as indicated by bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPAVGB67AMD64 Technology26569—Rev.
3.08—July 2007PAVGUSBPacked Average Unsigned BytesComputes the rounded-up average of each packed unsigned 8-bit integer value in the first sourceoperand and the corresponding packed 8-bit unsigned integer in the second source operand and writeseach average in the corresponding byte of the destination (first source). The average is computed byadding each pair of operands, adding 1 to the 9-bit temporary sum, and then right-shifting thetemporary sum by one bit position. The first source/destination operand is an MMX register. Thesecond source operand is another MMX register or 64-bit memory location.The PAVGUSB instruction performs a function identical to the 64-bit version of the PAVGBinstruction, although the two instructions have different opcodes.
PAVGUSB is a 3DNow! instruction.It is useful for pixel averaging in MPEG-2 motion compensation and video scaling operations.The PAVGUSB instruction is an AMD 3DNow!™ instruction. The presence of this instruction set isindicated by a CPUID feature bit. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionPAVGBMnemonicOpcodePAVGUSB mmx1, mmx2/mem640F 0F /r BFDescriptionAverages packed 8-bit unsigned integer values in anMMX register and another MMX register or 64-bitmemory location and writes the result in the destinationMMX register.mmx1mmx2/mem64630.....63.0......averageaveragepavgusb.eps68PAVGUSBInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyRelated InstructionsNonerFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by bit 31 in CPUID function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPAVGUSB69AMD64 Technology26569—Rev.
3.08—July 2007PAVGWPacked Average Unsigned WordsComputes the rounded average of each packed unsigned 16-bit integer value in the first source operandand the corresponding packed 16-bit unsigned integer in the second source operand and writes eachaverage in the corresponding word of the destination (first source). The average is computed by addingeach pair of operands, adding 1 to the 17-bit temporary sum, and then right-shifting the temporary sumby one bit position.
The first source/destination operand is an MMX register and the second sourceoperand is another MMX register or 64-bit memory location.The PAVGW instruction is a member of both the AMD MMX™ extensions and the SSE instructionsets. The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume3.)MnemonicOpcodePAVGW mmx1, mmx2/mem640F E3 /rDescriptionAverages packed 16-bit unsigned integer values in anMMX register and another MMX register or 64-bitmemory location and writes the result in thedestination MMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.averageaveragepavgw-64.epsRelated InstructionsPAVGBrFLAGS AffectedNone70PAVGWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to the MMX™ instruction set arenot supported, as indicated by EDX bit 22 of CPUIDfunction 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPAVGW71AMD64 Technology26569—Rev.
3.08—July 2007PCMPEQBPacked Compare Equal BytesCompares corresponding packed bytes in the first and second source operands and writes the result ofeach compare in the corresponding byte of the destination (first source). For each pair of bytes, if thevalues are equal, the result is all 1s.
If the values are not equal, the result is all 0s. The firstsource/destination operand is an MMX register and the second source operand is another MMXregister or 64-bit memory location.The PCMPEQB instruction is an MMX™ instruction. The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPEQB mmx1, mmx2/mem64DescriptionCompares packed bytes in an MMX register and anMMX register or 64-bit memory location.0F 74 /rmmx1....mmx2/mem64..630.....63.0......comparecompareall 1s or 0sall 1s or 0spcmpeqb-64.epsRelated InstructionsPCMPEQD, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTWrFLAGS AffectedNone72PCMPEQBInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by bit 23 in CPUID function 0000_0001h orfunction 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPCMPEQB73AMD64 Technology26569—Rev.
3.08—July 2007PCMPEQDPacked Compare Equal DoublewordsCompares corresponding packed 32-bit values in the first and second source operands and writes theresult of each compare in the corresponding 32 bits of the destination (first source). For each pair ofdoublewords, if the values are equal, the result is all 1s.
If the values are not equal, the result is all 0s.The first source/destination operand is an MMX register and the second source operand is anotherMMX register or 64-bit memory location.The PCMPEQD instruction is an MMX™ instruction. The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPEQD mmx1, mmx2/mem640F 76 /rDescriptionCompares packed doublewords in an MMX registerand an MMX register or 64-bit memory location.mmx163mmx2/mem6432 3106332 310comparecompareall 1s or 0sall 1s or 0spcmpeqd-64.epsRelated InstructionsPCMPEQB, PCMPEQW, PCMPGTB, PCMPGTD, PCMPGTWrFLAGS AffectedNone74PCMPEQDInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPCMPEQD75AMD64 Technology26569—Rev.
3.08—July 2007PCMPEQWPacked Compare Equal WordsCompares corresponding packed 16-bit values in the first and second source operands and writes theresult of each compare in the corresponding 16 bits of the destination (first source). For each pair ofwords, if the values are equal, the result is all 1s. If the values are not equal, the result is all 0s.
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