Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 13
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(See “CPUID” in Volume 3.)MnemonicOpcodePADDUSB mmx1, mmx2/mem640F DC /rDescriptionAdds packed byte unsigned integer values in anMMX register and another MMX register or 64-bitmemory location and writes the result in thedestination MMX register.mmx1....mmx2/mem64..630.....63.0......addsaturateaddsaturatepaddusb-64.epsRelated InstructionsPADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSW, PADDWrFLAGS AffectedNone56PADDUSBInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPADDUSB57AMD64 Technology26569—Rev.
3.08—July 2007PADDUSWPacked Add Unsigned with Saturation WordsAdds each packed 16-bit unsigned integer value in the first source operand to the correspondingpacked 16-bit unsigned integer in the second source operand and writes the unsigned integer result ofeach addition in the corresponding word of the destination (first source). The first source/destinationoperand is an MMX register and the second source operand is another MMX register or 64-bit memorylocation.For each packed value in the destination, if the value is larger than the largest unsigned 16-bit integer,it is saturated to FFFFh, and if the value is smaller than the smallest unsigned 16-bit integer, it issaturated to 0000h.The PADDUSW instruction is an MMX™ instruction. The presence of this instruction set is indicatedby a CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePADDUSW mmx1, mmx2/mem640F DD /rDescriptionAdds packed 16-bit unsigned integer values in anMMX register and another MMX register or 64-bitmemory location and writes result in the destinationMMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.addsaturateaddsaturatepaddusw-64.epsRelated InstructionsPADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDWrFLAGS AffectedNone58PADDUSWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPADDUSW59AMD64 Technology26569—Rev.
3.08—July 2007PADDWPacked Add WordsAdds each packed 16-bit integer value in the first source operand to the corresponding packed 16-bitinteger in the second source operand and writes the integer result of each addition in the correspondingword of the destination (first source). The first source/destination operand is an MMX register and thesecond source operand is another MMX register or 64-bit memory location.This instruction operates on both signed and unsigned integers. If the result overflows, the carry isignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 16 bits of theresult are written in the destination.The PADDW instruction is an MMX™ instruction. The presence of this instruction set is indicated bya CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePADDW mmx1, mmx2/mem640F FD /rDescriptionAdds packed 16-bit integer values in an MMX registerand another MMX register or 64-bit memory locationand writes the result in the destination MMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.addaddpaddw-64.epsRelated InstructionsPADDB, PADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSWrFLAGS AffectedNone60PADDWInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPADDW61AMD64 Technology26569—Rev.
3.08—July 2007PANDPacked Logical Bitwise ANDPerforms a bitwise logical AND of the values in the first and second source operands and writes theresult in the destination (first source). The first source/destination operand is an MMX register and thesecond source operand is another MMX register or 64-bit memory location.The PAND instruction is an MMX™ instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePAND mmx1, mmx2/mem640F DB /rDescriptionPerforms bitwise logical AND of values in an MMXregister and in another MMX register or 64-bit memorylocation and writes the result in the destination MMXregister.mmx1mmx2/mem64063630ANDpand-64.epsRelated InstructionsPANDN, POR, PXORrFLAGS AffectedNone62PANDInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function 0000_0001hor function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDPage fault, #PFx87 floating-pointexception pending,#MFAlignment check, #ACInstruction ReferenceXPAND63AMD64 Technology26569—Rev.
3.08—July 2007PANDNPacked Logical Bitwise AND NOTPerforms a bitwise logical AND of the value in the second source operand and the one’s complementof the value in the first source operand and writes the result in the destination (first source). The firstsource/destination operand is an MMX register and the second source operand is another MMXregister or 64-bit memory location.The PANDN instruction is an MMX™ instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePANDN mmx1, mmx2/mem640F DF /rDescriptionPerforms bitwise logical AND NOT of values in an MMXregister and in another MMX register or 64-bit memorylocation and writes the result in the destination MMXregister.mmx1mmx2/mem64063630invertANDpandn-64.epsRelated InstructionsPAND, POR, PXORrFLAGS AffectedNone64PANDNInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function 0000_0001hor function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDPage fault, #PFx87 floating-pointexception pending,#MFAlignment check, #ACInstruction ReferenceXPANDN65AMD64 Technology26569—Rev.
3.08—July 2007PAVGBPacked Average Unsigned BytesComputes the rounded average of each packed unsigned 8-bit integer value in the first source operandand the corresponding packed 8-bit unsigned integer in the second source operand and writes eachaverage in the corresponding byte of the destination (first source). The average is computed by addingeach pair of operands, adding 1 to the 9-bit temporary sum, and then right-shifting the temporary sumby one bit position. The destination and source operands are an MMX register and another MMXregister or 64-bit memory location.The PAVGB instruction is a member of both the AMD MMX™ extensions and the SSE instructionsets. The presence of this instruction set is indicated by CPUID feature bits.
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