Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 8
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(See “CPUID” in Volume 3.) Support for misaligned 16-byte memory accesses isindicated by CPUID feature bit ECX[7] of function 8000_0001h.MnemonicOpcodeCVTTPD2PI mmx, xmm/mem128Description66 0F 2C /rConverts packed double-precision floating-pointvalues in an XMM register or 128-bit memory locationto packed doubleword integer values in thedestination MMX register. Inexact results aretruncated.mmx6332 31xmm/mem128012764 63convert0convertcvttpd2pi.epsRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ,CVTTSD2SIrFLAGS AffectedNone12CVTTPD2PIInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that can be set to one or zero is M (modified).
Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM = 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM = 1.XXAn exception is pending due to an x87 floating-pointinstruction.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPXx87 floating-pointexception pending, #MFSIMD Floating-PointException, #XFInstruction ReferenceXXXCVTTPD2PI13AMD64 TechnologyException26569—Rev.
3.08—July 2007RealVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)14XXXA source operand was an SNaN value, a QNaN value,or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTTPD2PIInstruction Reference26569—Rev.
3.08—July 2007CVTTPS2PIAMD64 TechnologyConvert Packed Single-Precision Floating-Point toPacked Doubleword Integers, TruncatedConverts two packed single-precision floating-point values in the low-order 64 bits of an XMMregister or a 64-bit memory location to two packed 32-bit signed integer values and writes theconverted values in an MMX register.If the result of the conversion is an inexact value, the value is truncated (rounded toward zero). If thefloating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximumsigned doubleword (–231 to +231 – 1), the instruction returns the 32-bit indefinite integer value(8000_0000h) when the invalid-operation exception (IE) is masked.The CVTTPS2PI instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTTPS2PI mmx, xmm/mem640F 2C /rDescriptionConverts packed single-precision floating-point values inan XMM register or 64-bit memory location to doublewordinteger values in the destination MMX register. Inexactresults are truncated.mmx6332 31xmm/mem64012764 6332 31convert0convertcvttps2pi.epsRelated InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ,CVTTSS2SIrFLAGS AffectedNoneInstruction ReferenceCVTTPS2PI15AMD64 Technology26569—Rev. 3.08—July 2007MXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFXAlignment check, #ACSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)16XXXA source operand was an SNaN value, a QNaN value,or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTTPS2PIInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyEMMSExit Multimedia StateClears the MMX state by setting the state of the x87 stack registers to empty (tag-bit encoding of all 1sfor all MMX registers) indicating that the contents of the registers are available for a new procedure,such as an x87 floating-point procedure. This setting of the tag bits is referred to as “clearing the MMXstate”.Because the MMX registers and tag word are shared with the x87 floating-point instructions, softwareshould execute an EMMS instruction to clear the MMX state before executing code that includes x87floating-point instructions.The functions of the EMMS and FEMMS instructions are identical.For details about the setting of x87 tag bits, see “Media and x87 Processor State” in Volume 2.The EMMS instruction is an MMX™ instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeEMMSDescription0F 77Clears the MMX state.Related InstructionsFEMMS (a 3DNow! instruction)rFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available, #NMXXXThe task-switch bit (TS) of CR0 was set to 1.x87 floating-pointexception pending, #MFXXXAn unmasked x87 floating-point exception waspending.Invalid opcode, #UDInstruction ReferenceEMMS17AMD64 Technology26569—Rev.
3.08—July 2007FEMMSFast Exit Multimedia StateClears the MMX state by setting the state of the x87 stack registers to empty (tag-bit encoding of all 1sfor all MMX registers) indicating that the contents of the registers are available for a new procedure,such as an x87 floating-point procedure. This setting of the tag bits is referred to as “clearing the MMXstate”.Because the MMX registers and tag word are shared with the x87 floating-point instructions, softwareshould execute an EMMS or FEMMS instruction to clear the MMX state before executing code thatincludes x87 floating-point instructions.FEMMS is a 3DNow! instruction.
The functions of the FEMMS and EMMS instructions are identical.The FEMMS instruction is supported for backward-compatibility with certain AMD processors.Software that must be both compatible with both AMD and non-AMD processors should use theEMMS instruction. Check the status of EDX bit 31 returned by CPUID function 8000_0001h to verifythat the processor supports this function. (See “CPUID” in Volume 3.)For details about the setting of x87 tag bits, see “Media and x87 Processor State” in Volume 2.AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionEMMSMnemonicOpcodeFEMMS0F 0EDescriptionClears MMX state.Related InstructionsEMMSrFLAGS AffectedNoneExceptionsExceptionInvalid opcode, #UD18RealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are notsupported, as indicated by EDX bit 31 in CPUIDfunction 8000_0001h.FEMMSInstruction Reference26569—Rev.
3.08—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionDevice not available, #NMXXXThe task-switch bit (TS) of CR0 was set to 1.x87 floating-point exceptionpending, #MFXXXAn unmasked x87 floating-point exception waspending.Instruction ReferenceFEMMS19AMD64 Technology26569—Rev. 3.08—July 2007FRSTORFloating-Point Restore x87 and MMX™ StateRestores the complete x87 state from memory starting at the specified address, as stored by a previouscall to FNSAVE.
The x87 state occupies 94 or 108 bytes of memory depending on whether theprocessor is operating in real or protected mode and whether the operand-size attribute is 16-bit or 32bit. Because the MMX registers are mapped onto the low 64 bits of the x87 floating-point registers,this operation also restores the MMX state.If FRSTOR results in set exception flags in the loaded x87 status word register, and these exceptionsare unmasked in the x87 control word register, a floating-point exception occurs when the nextfloating-point instruction is executed (except for the no-wait floating-point instructions).To avoid generating exceptions when loading a new environment, use the FCLEX or FNCLEXinstruction to clear the exception flags in the x87 status word before storing that environment.For details about the memory image restored by FRSTOR, see “Media and x87 Processor State” inVolume 2.MnemonicFRSTORmem94/108envOpcodeDescriptionDD /4Load the x87 state from mem94/108env.Related InstructionsFSAVE, FNSAVE, FXSAVE, FXRSTORrFLAGS AffectedNonex87 Condition Codex87 Condition CodeValueDescriptionC0MLoaded from memory.C1MLoaded from memory.C2MLoaded from memory.C3MLoaded from memory.Note: A flag set to 1 or cleared to 0 is M (modified).
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