Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 9
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Unaffected flags are blank. Undefined flags are U.20FRSTORInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or wasnon-canonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXAn unmasked x87 floating-point exception was pending.x87 floating-pointexception pending,#MFXInstruction ReferenceFRSTOR21AMD64 Technology26569—Rev.
3.08—July 2007FSAVE(FNSAVE)Floating-Point Save x87 and MMX StateStores the complete x87 state to memory starting at the specified address and reinitializes the x87 state.The x87 state requires 94 or 108 bytes of memory, depending upon whether the processor is operatingin real or protected mode and whether the operand-size attribute is 16-bit or 32-bit. Because the MMXregisters are mapped onto the low 64 bits of the x87 floating-point registers, this operation also savesthe MMX state. For details about the memory image saved by FNSAVE, see “Media and x87Processor State” in Volume 2.The FNSAVE instruction does not wait for pending unmasked x87 floating-point exceptions to beprocessed.
Processor interrupts should be disabled before using this instruction.Assemblers usually provide an FSAVE macro that expands into the instruction sequence:WAITFNSAVE destination; Opcode 9B; Opcode DD /6The WAIT (9Bh) instruction checks for pending x87 exceptions and calls an exception handler, ifnecessary. The FNSAVE instruction then stores the x87 state to the specified destination.MnemonicOpcodeDescriptionFNSAVEmem94/108envDD /6Copy the x87 state to mem94/108env without checking forpending floating-point exceptions, then reinitialize the x87state.FSAVE mem94/108env9B DD /6Copy the x87 state to mem94/108env after checking forpending floating-point exceptions, then reinitialize the x87state.Related InstructionsFRSTOR, FXSAVE, FXRSTORrFLAGS AffectedNonex87 Condition Codex87 Condition CodeValueC00C10C20C3022DescriptionFSAVE (FNSAVE)Instruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or wasnon-canonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.Instruction ReferenceFSAVE (FNSAVE)23AMD64 Technology26569—Rev.
3.08—July 2007FXRSTORRestore XMM, MMX™, and x87 StateRestores the XMM, MMX, and x87 state. The data loaded from memory is the state informationpreviously saved using the FXSAVE instruction. Restoring data with FXRSTOR that had beenpreviously saved with an FSAVE (rather than FXSAVE) instruction results in an incorrect restoration.If FXRSTOR results in set exception flags in the loaded x87 status word register, and these exceptionsare unmasked in the x87 control word register, a floating-point exception occurs when the nextfloating-point instruction is executed (except for the no-wait floating-point instructions).If the restored MXCSR register contains a set bit in an exception status flag, and the correspondingexception mask bit is cleared (indicating an unmasked exception), loading the MXCSR register doesnot cause a SIMD floating-point exception (#XF).FXRSTOR does not restore the x87 error pointers (last instruction pointer, last data pointer, and lastopcode), except in the relatively rare cases in which the exception-summary (ES) bit in the x87 statusword is set to 1, indicating that an unmasked x87 exception has occurred.The architecture supports two 512-bit memory formats for FXRSTOR, a 64-bit format that loadsXMM0-XMM15, and a 32-bit legacy format that loads only XMM0-XMM7.
If FXRSTOR is executedin 64-bit mode, the 64-bit format is used, otherwise the 32-bit format is used. When the 64-bit formatis used, if the operand-size is 64-bit, FXRSTOR loads the x87 pointer registers as offset64, otherwise itloads them as sel:offset32.
For details about the memory format used by FXRSTOR, see "SavingMedia and x87 Processor State" in Volume 2. For details about the memory image restored byFXRSTOR, see “Saving Media and x87 Processor State” in Volume 2.If the fast-FXSAVE/FXRSTOR (FFXSR) feature is enabled in EFER, FXRSTOR does not restore theXMM registers (XMM0-XMM15) when executed in 64-bit mode at CPL 0. MXCSR is restoredwhether fast-FXSAVE/FXRSTOR is enabled or not.
Software can check EDX bit 24 returned byCPUID function 0000_0001h or function 8000_0001h to determine whether the fastFXSAVE/FXRSTOR feature is available. (See “CPUID” in Volume 3.)If the operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0, the savedimage of XMM0–XMM15 and MXCSR is not loaded into the processor. A general-protectionexception occurs if the FXRSTOR instruction attempts to load non-zero values into reserved MXCSRbits. Software can use MXCSR_MASK to determine which bits of MXCSR are reserved. For detailson the MXCSR_MASK, see “128-Bit, 64-Bit, and x87 Programming” in Volume 2..MnemonicFXRSTOR mem512envOpcode0F AE /1DescriptionRestores XMM, MMX™, and x87 state from 512-bytememory location.Related InstructionsFWAIT, FXSAVE24FXRSTORInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyrFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCMMM171514PMUMOMZMDMIMDAZPEUEOEZEDEIEMMMMMMMMMMMMMM131211109876543210Note: A flag that can be set to one or zero is M (modified).
Unaffected flags are blank. Shaded fields are reserved.ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe FXSAVE/FXRSTOR instructions are notsupported, as indicated by EDX bit 24 of CPUIDfunction 0000_0001h or function 8000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit,or was non-canonical.XXXA memory address exceeded the data segment limitor was non-canonical.XA null data segment was used to reference memory.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFInstruction ReferenceXXXThe memory operand was not aligned on a 16-byteboundary.XXXOnes were written to the reserved bits in MXCSR.XXA page fault resulted from the execution of theinstruction.FXRSTOR25AMD64 Technology26569—Rev. 3.08—July 2007FXSAVESave XMM, MMX, and x87 StateSaves the XMM, MMX, and x87 state.
A memory location that is not aligned on a 16-byte boundarycauses a general-protection exception.Unlike FSAVE and FNSAVE, FXSAVE does not alter the x87 tag bits. The contents of the savedMMX/x87 data registers are retained, thus indicating that the registers may be valid (or whatever othervalue the x87 tag bits indicated prior to the save). To invalidate the contents of the MMX/x87 dataregisters after FXSAVE, software must execute an FINIT instruction. Also, FXSAVE (like FNSAVE)does not check for pending unmasked x87 floating-point exceptions. An FWAIT instruction can beused for this purpose.FXSAVE does not save the x87 pointer registers (last instruction pointer, last data pointer, and lastopcode), except in the relatively rare cases in which the exception-summary (ES) bit in the x87 statusword is set to 1, indicating that an unmasked x87 exception has occurred.The architecture supports two 512-bit memory formats for FXSAVE, a 64-bit format that savesXMM0-XMM15, and a 32-bit legacy format that saves only XMM0-XMM7.
If FXSAVE is executedin 64-bit mode, the 64-bit format is used, otherwise the 32-bit format is used. When the 64-bit format isused, if the operand-size is 64-bit, FXSAVE saves the x87 pointer registers as offset64, otherwise itsaves them as sel:offset32. For more details about the memory format used by FXSAVE, see “SavingMedia and x87 Processor State” in Volume 2.If the fast-FXSAVE/FXRSTOR (FFXSR) feature is enabled in EFER, FXSAVE does not save theXMM registers (XMM0-XMM15) when executed in 64-bit mode at CPL 0. MXCSR is saved whetherfast-FXSAVE/FXRSTOR is enabled or not.
Software can check EDX bit 24 returned by CPUIDfunction 0000_0001h or function 8000_0001h to determine whether the fast-FXSAVE/FXRSTORfeature is available. (See “CPUID” in Volume 3.)If the operating-system FXSAVE/FXRSTOR support bit (OSFXSR) of CR4 is cleared to 0, FXSAVEdoes not save the image of XMM0–XMM15 or MXCSR. For details about the CR4.OSFXSR bit, see“FXSAVE/FXRSTOR Support (OSFXSR) Bit” in Volume 2.MnemonicFXSAVE mem512envOpcode0F AE /0DescriptionSaves XMM, MMX, and x87 state to 512-byte memorylocation.Related InstructionsFINIT, FNSAVE, FRSTOR, FSAVE, FXRSTOR, LDMXCSR, STMXCSRrFLAGS AffectedNone26FXSAVEInstruction Reference26569—Rev.
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