Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 11
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3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by bit 23 in CPUID function 0000_0001h orfunction 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeds the stack segment limit oris non-canonical.XXXA memory address exceeded the stack segment limitor was non-canonical.XA null data segment was used to reference memory.XThe destination operand was in a non-writablesegment.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFx87 floating-pointexception pending,#MFAlignment check, #AC38XMOVQInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyMOVQ2DQMove Quadword to QuadwordMoves a 64-bit value from an MMX register to the low-order 64 bits of an XMM register, with zeroextension to 128 bits.The MOVQ2DQ instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMOVQ2DQ xmm, mmxF3 0F D6 /rDescriptionMoves 64-bit value from an MMX register to an XMM register.xmm127mmx64 6306300copymovq2dq.epsRelated InstructionsMOVD, MOVDQA, MOVDQU, MOVDQ2Q, MOVQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.XXXThe SSE2 instructions are not supported, as indicatedby bit 26 in CPUID function 0000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception waspending.Invalid opcode, #UDInstruction ReferenceMOVQ2DQ39AMD64 TechnologyPACKSSDW26569—Rev.
3.08—July 2007Pack with Saturation Signed Doubleword to WordConverts each 32-bit signed integer in the first and second source operands to a 16-bit signed integerand packs the converted values into words in the destination (first source). The first source/destinationoperand is an MMX register and the second source operand is another MMX register or 64-bit memorylocation.Converted values from the first source operand are packed into the low-order words of the destination,and the converted values from the second source operand are packed into the high-order words of thedestination.For each packed value in the destination, if the value is larger than the largest signed 16-bit integer, it issaturated to 7FFFh, and if the value is smaller than the smallest signed 16-bit integer, it is saturated to8000h.The PACKSSDW instruction is an MMX™ instruction.
The presence of this instruction set isindicated by a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePACKSSDW mmx1, mmx2/mem640F 6B /rDescriptionPacks 32-bit signed integers in an MMX registerand another MMX register or 64-bit memorylocation into 16-bit signed integers in an MMXregister.mmx16332 31convertmmx2/mem64063convertconvert63 48 47 32 31 16 15032 310convertpackssdw-64.epsRelated InstructionsPACKSSWB, PACKUSWB40PACKSSDWInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPACKSSDW41AMD64 Technology26569—Rev.
3.08—July 2007PACKSSWBPack with Saturation Signed Word to ByteConverts each 16-bit signed integer in the first and second source operands to an 8-bit signed integerand packs the converted values into bytes in the destination (first source).
The first source/destinationoperand is an MMX register and the second source operand is another MMX register or 64-bit memorylocation.Converted values from the first source operand are packed into the low-order bytes of the destination,and the converted values from the second source operand are packed into the high-order bytes of thedestination.For each packed value in the destination, if the value is larger than the largest signed 8-bit integer, it issaturated to 7Fh, and if the value is smaller than the smallest signed 8-bit integer, it is saturated to 80h.The PACKSSWB instruction is an MMX instruction.
The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePACKSSWB mmx1, mmx2/mem64DescriptionPacks 16-bit signed integers in an MMX registerand another MMX register or 64-bit memorylocation into 8-bit signed integers in an MMXregister.0F 63 /rmmx16348 47mmx2/mem6432 31.convert16 15.063convertconvert.63..32 3148 4732 31.16 150.convert.0packsswb-64.epsRelated InstructionsPACKSSDW, PACKUSWBrFLAGS AffectedNone42PACKSSWBInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPACKSSWB43AMD64 Technology26569—Rev.
3.08—July 2007PACKUSWBPack with Saturation Signed Word to UnsignedByteConverts each 16-bit signed integer in the first and second source operands to an 8-bit unsigned integerand packs the converted values into bytes in the destination (first source). The first source/destinationoperand is an MMX register and the second source operand is another MMX register or 64-bit memorylocation.Converted values from the first source operand are packed into the low-order bytes of the destination,and the converted values from the second source operand are packed into the high-order bytes of thedestination.For each packed value in the destination, if the value is larger than the largest unsigned 8-bit integer, itis saturated to FFh, and if the value is smaller than the smallest unsigned 8-bit integer, it is saturated to00h.The PACKUSWB instruction is an MMX™ instruction.
The presence of this instruction set isindicated by a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePACKUSWB mmx1, mmx2/mem64DescriptionPacks 16-bit signed integers in an MMX registerand another MMX register or 64-bit memorylocation into 8-bit unsigned integers in an MMXregister.0F 67 /rmmx16348 47mmx2/mem6432 31.convert16 15.063convertconvert.63..32 3148 4732 31.16 150.convert.0packuswb-64.epsRelated InstructionsPACKSSDW, PACKSSWB44PACKUSWBInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPACKUSWB45AMD64 Technology26569—Rev.
3.08—July 2007PADDBPacked Add BytesAdds each packed 8-bit integer value in the first source operand to the corresponding packed 8-bitinteger in the second source operand and writes the integer result of each addition in the correspondingbyte of the destination (first source). The first source/destination operand is an MMX register and thesecond source operand is another MMX register or 64-bit memory location.The PADDB instruction operates on both signed and unsigned integers. If the result overflows, thecarry is ignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 8 bits ofeach result are written in the destination.The PADDB instruction is an MMX™ instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDB mmx1, mmx2/mem640F FC /rDescriptionAdds packed byte integer values in an MMX registerand another MMX register or 64-bit memory locationand writes the result in the destination MMX register.mmx1....mmx2/mem64..630.....63.0......addaddpaddb-64.epsRelated InstructionsPADDD, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDWrFLAGS AffectedNone46PADDBInstruction Reference26569—Rev.
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