Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 7
Текст из файла (страница 7)
3.08—July 2007CVTPD2PIAMD64 TechnologyConvert Packed Double-Precision Floating-Point toPacked Doubleword IntegersConverts two packed double-precision floating-point values in an XMM register or a 128-bit memorylocation to two packed 32-bit signed integer values and writes the converted values in an MMXregister.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register. If the floating-point value is a NaN, infinity, or if the result ofthe conversion is larger than the maximum signed doubleword (–231 to +231 – 1), the instructionreturns the 32-bit indefinite integer value (8000_0000h) when the invalid-operation exception (IE) ismasked.The CVTPD2PI instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.) Support for misaligned 16-byte memory accesses isindicated by CPUID feature bit ECX[7] of function 8000_0001h.MnemonicOpcodeCVTPD2PI mmx, xmm2/mem128Description66 0F 2D /rConverts packed double-precision floating-pointvalues in an XMM register or 128-bit memory locationto packed doubleword integers values in thedestination MMX register.mmx6332 31xmm/mem128012764 63convert0convertcvtpd2pi.epsRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPI2PD, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI,CVTTSD2SIrFLAGS AffectedNoneInstruction ReferenceCVTPD2PI3AMD64 Technology26569—Rev.
3.08—July 2007MXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM = 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM = 1.General protection, #GPXx87 floating-pointexception pending, #MFXXXAn exception is pending due to an x87 floating-pointinstruction.SIMD Floating-PointException, #XFXXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.4CVTPD2PIInstruction Reference26569—Rev.
3.08—July 2007ExceptionRealAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTPD2PI5AMD64 TechnologyCVTPI2PD26569—Rev. 3.08—July 2007Convert Packed Doubleword Integers to PackedDouble-Precision Floating-PointConverts two packed 32-bit signed integer values in an MMX register or a 64-bit memory location totwo double-precision floating-point values and writes the converted values in an XMM register.The CVTPI2PD instruction is an SSE2 instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTPI2PD xmm, mmx/mem6466 0F 2A /rDescriptionConverts two packed doubleword integer values in anMMX register or 64-bit memory location to two packeddouble-precision floating-point values in the destinationXMM register.xmm12764 63mmx/mem6406332 310convertconvertcvtpi2pd.epsRelated InstructionsCVTDQ2PD, CVTPD2DQ, CVTPD2PI, CVTSD2SI, CVTSI2SD, CVTTPD2DQ, CVTTPD2PI,CVTTSD2SIrFLAGS AffectedNoneMXCSR Flags AffectedNone6CVTPI2PDInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsRealVirtual8086ProtectedXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performedwhile alignment checking was enabled.ExceptionInvalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXCause of ExceptionCVTPI2PD7AMD64 TechnologyCVTPI2PS26569—Rev.
3.08—July 2007Convert Packed Doubleword Integers to PackedSingle-Precision Floating-PointConverts two packed 32-bit signed integer values in an MMX register or a 64-bit memory location totwo single-precision floating-point values and writes the converted values in the low-order 64 bits ofan XMM register. The high-order 64 bits of the XMM register are not modified.The CVTPI2PS instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeCVTPI2PS xmm, mmx/mem64DescriptionConverts packed doubleword integer values in an MMXregister or 64-bit memory location to single-precisionfloating-point values in the destination XMM register.0F 2A /rxmm127mmx/mem6464 6332 3106332 310convertconvertcvtpi2ps.epsRelated InstructionsCVTDQ2PS, CVTPS2DQ, CVTPS2PI, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI,CVTTSS2SIrFLAGS AffectedNoneMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEIE43210M1715141312111098765Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank.8CVTPI2PSInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionInvalid opcode, #UDRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFXAlignment check, #ACSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsPrecision exception(PE)Instruction ReferenceXXXA result could not be represented exactly in thedestination format.CVTPI2PS9AMD64 TechnologyCVTPS2PI26569—Rev.
3.08—July 2007Convert Packed Single-Precision Floating-Point toPacked Doubleword IntegersConverts two packed single-precision floating-point values in the low-order 64 bits of an XMMregister or a 64-bit memory location to two packed 32-bit signed integers and writes the convertedvalues in an MMX register.If the result of the conversion is an inexact value, the value is rounded as specified by the roundingcontrol bits (RC) in the MXCSR register.
If the floating-point value is a NaN, infinity, or if the result ofthe conversion is larger than the maximum signed doubleword (–231 to +231 – 1), the instructionreturns the 32-bit indefinite integer value (8000_0000h) when the invalid-operation exception (IE) ismasked.The CVTPS2PI instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeCVTPS2PI mmx,xmm/mem640F 2D /rDescriptionConverts packed single-precision floating-point values in anXMM register or 64-bit memory location to packeddoubleword integers in the destination MMX register.mmx6332 31xmm/mem64012764 6332 31convert0convertcvtps2pi.epsRelated InstructionsCVTDQ2PS, CVTPI2PS, CVTPS2DQ, CVTSI2SS, CVTSS2SI, CVTTPS2DQ, CVTTPS2PI,CVTTSS2SIrFLAGS AffectedNone10CVTPS2PIInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyMXCSR Flags AffectedMMFZRCPMUMOMZMDMIMDAZPEUEOEZEDEM1715141312111098765IEM43210Note: A flag that can be set to one or zero is M (modified). Unaffected flags are blank.ExceptionsExceptionInvalid opcode, #UDRealVirtual8086ProtectedCause of ExceptionXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 was cleared to 0.XXXThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was cleared to0.See SIMD Floating-Point Exceptions, below, fordetails.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performedwhile alignment checking was enabled.XThere was an unmasked SIMD floating-pointexception while CR4.OSXMMEXCPT was set to 1.See SIMD Floating-Point Exceptions, below, fordetails.General protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFXAlignment check, #ACSIMD Floating-PointException, #XFXXSIMD Floating-Point ExceptionsInvalid-operationexception (IE)Precision exception(PE)Instruction ReferenceXXXA source operand was an SNaN value, a QNaNvalue, or ±infinity.XXXA source operand was too large to fit in thedestination format.XXXA result could not be represented exactly in thedestination format.CVTPS2PI11AMD64 Technology26569—Rev.
3.08—July 2007CVTTPD2PI Convert Packed Double-Precision Floating-Point toPacked Doubleword Integers, TruncatedConverts two packed double-precision floating-point values in an XMM register or a 128-bit memorylocation to two packed 32-bit signed integer values and writes the converted values in an MMXregister.If the result of the conversion is an inexact value, the value is truncated (rounded toward zero).
If thefloating-point value is a NaN, infinity, or if the result of the conversion is larger than the maximumsigned doubleword (–231 to +231 – 1), the instruction returns the 32-bit indefinite integer value(8000_0000h) when the invalid-operation exception (IE) is masked.The CVTTPD2PI instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit.
![](https://s.studizba.com/z.php?f=/templates/si/i/noavatar.png&w=100&h=100&t=1"){kind=avatar}
