Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 10
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3.08—July 2007AMD64 TechnologyMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe FXSAVE/FXRSTOR instructions are notsupported, as indicated by bit 24 of CPUID function0000_0001h or function 8000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit,or was non-canonical.XXXA memory address exceeded the data segment limitor was non-canonical.XA null data segment was used to reference memory.XThe memory operand was not aligned on a 16-byteboundary.XThe destination operand was in a non-writablesegment.XA page fault resulted from the execution of theinstruction.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFInstruction ReferenceXXXFXSAVE27AMD64 Technology26569—Rev. 3.08—July 2007MASKMOVQMasked Move QuadwordStores bytes from the first source operand, as selected by the second source operand, to a memorylocation specified in the DS:rDI registers (except that DS is ignored in 64-bit mode).
The first sourceoperand is an MMX register, and the second source operand is another MMX register. The mostsignificant bit (msb) of each byte in the second source operand specifies the store (1 = store, 0 = nostore) of the corresponding byte of the first source operand.A mask value of all 0s results in the following behavior:No data is written to memory.Page faults and exceptions associated with memory addressing are not guaranteed to be generatedin all implementations.Data breakpoints are not guaranteed to be generated in all implementations (although codebreakpoints are guaranteed).•••MASKMOVQ implicitly uses weakly-ordered, write-combining buffering for the data, as described in“Buffering and Combining Memory Writes” in Volume 2. If the stored data is shared by multipleprocessors, this instruction should be used together with a fence instruction in order to ensure datacoherency (refer to “Cache and TLB Management” in Volume 2).The MASKMOVQ instruction is an AMD extension to MMX™ instruction set and is an SSEinstruction.
The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” inVolume 3.)MnemonicMASKMOVQ mmx1, mmx228Opcode0F F7 /rDescriptionStore bytes from an MMX register, selected by the mostsignificant bit of the corresponding byte in another MMXregister, to DS:rDI.MASKMOVQInstruction Reference26569—Rev. 3.08—July 2007AMD64 Technologymmx1mmx2630............63 55 47 39 31 23 15 7 0......selectselectstore addressDS:rDImaskmovq.epsMemoryRelated InstructionsMASKMOVDQUExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR support bit(OSFXSR) of CR4 was cleared to 0.Invalid opcode, #UDXXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; and theAMD extensions to the MMX™ instruction set are notsupported, as indicated by EDX bit 22 of CPUIDfunction 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XA page fault resulted from the execution of theinstruction.Page fault, #PFInstruction ReferenceXMASKMOVQ29AMD64 TechnologyExceptionx87 floating-pointexception pending,#MFAlignment check, #AC3026569—Rev.
3.08—July 2007RealXVirtual8086 ProtectedCause of ExceptionXXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.MASKMOVQInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyMOVDMove Doubleword or QuadwordMoves a 32-bit or 64-bit value in one of the following ways:••••from a 32-bit or 64-bit general-purpose register or memory location to the low-order 32 or 64 bitsof an XMM register, with zero-extension to 128 bitsfrom the low-order 32 or 64 bits of an XMM to a 32-bit or 64-bit general-purpose register ormemory locationfrom a 32-bit or 64-bit general-purpose register or memory location to the low-order 32 bits (withzero-extension to 64 bits) or the full 64 bits of an MMX registerfrom the low-order 32 or the full 64 bits of an MMX register to a 32-bit or 64-bit general-purposeregister or memory location.The MOVD instruction is a member of both the MMX and the SSE2 instruction sets.
The presence ofthis instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVD mmx, reg/mem320F 6E /rMove 32-bit value from a general-purpose register or32-bit memory location to an MMX register.MOVD mmx, reg/mem640F 6E /rMove 64-bit value from a general-purpose register or64-bit memory location to an MMX register.MOVD reg/mem32, mmx0F 7E /rMove 32-bit value from an MMX register to a 32-bitgeneral-purpose register or memory location.MOVD reg/mem64, mmx0F 7E /rMove 64-bit value from an MMX register to a 64-bitgeneral-purpose register or memory location.The following diagrams illustrate the operation of the MOVD instruction.Instruction ReferenceMOVD31AMD64 Technology26569—Rev. 3.08—July 2007xmmreg/mem3212732 3131000xmm127reg/mem6464 6363000with REX prefixreg/mem32All operationsare "copy"310xmm12732 31reg/mem64630xmm012764 630with REX prefixmmx6332 31reg/mem3231000mmx63reg/mem640630with REX prefixreg/mem3231mmx063reg/mem64630mmx063with REX prefix3232 31MOVD0movd.epsInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyRelated InstructionsMOVDQA, MOVDQU, MOVDQ2Q, MOVQ, MOVQ2DQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsRealVirtual8086ProtectedXXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 of CPUID function0000_0001h.XXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 of CPUID function 0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe instruction used XMM registers whileCR4.OSFXSR=0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XThe destination operand was in a non-writablesegment.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.ExceptionInvalid opcode, #UDGeneral protection,#GPPage fault, #PFx87 floating-pointexception pending,#MFAlignment check, #ACInstruction ReferenceXDescriptionMOVD33AMD64 Technology26569—Rev.
3.08—July 2007MOVDQ2QMove Quadword to QuadwordMoves the low-order 64-bit value in an XMM register to a 64-bit MMX register.The MOVDQ2Q instruction is an SSE2 instruction. The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeMOVDQ2Q mmx, xmmDescriptionMoves low-order 64-bit value from an XMM register to thedestination MMX register.F2 0F D6 /rmmxxmm63012764 630copymovdq2q.epsRelated InstructionsMOVD, MOVDQA, MOVDQU, MOVQ, MOVQ2DQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE2 instructions are not supported, as indicatedby EDX bit 26 in CPUID function 0000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.General protection,#GPXXXThe destination operand was in non-writable segment.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception waspending.Invalid opcode, #UD34MOVDQ2QInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyMOVNTQMove Non-Temporal QuadwordStores a 64-bit MMX register value into a 64-bit memory location. This instruction indicates to theprocessor that the data is non-temporal, and is unlikely to be used again soon. The processor treats thestore as a write-combining (WC) memory write, which minimizes cache pollution. The exact methodby which cache pollution is minimized depends on the hardware implementation of the instruction. Forfurther information, see “Memory Optimization” in Volume 1.MOVNTQ is weakly-ordered with respect to other instructions that operate on memory.
Softwareshould use an SFENCE instruction to force strong memory ordering of MOVNTQ with respect toother stores.MOVNTQ implicitly uses weakly-ordered, write-combining buffering for the data, as described in“Buffering and Combining Memory Writes” in Volume 2. For data that is shared by multipleprocessors, this instruction should be used together with a fence instruction in order to ensure datacoherency (refer to “Cache and TLB Management” in Volume 2).The MOVD instruction is a member of both the AMD MMX extensions and the SSE instruction sets.The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodeMOVNTQ mem64, mmxDescriptionStores a 64-bit MMX register value into a 64-bit memorylocation, minimizing cache pollution.0F E7 /rmem6463mmx6300copymovntq.epsRelated InstructionsMOVNTDQ, MOVNTI, MOVNTPD, MOVNTPSInstruction ReferenceMOVNTQ35AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; and theAMD extensions to the MMX™ instruction set are notsupported, as indicated by EDX bit 22 of CPUIDfunction 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XThe destination operand was in a non-writablesegment.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection,#GPPage fault, #PFx87 floating-pointexception pending,#MFAlignment check, #AC36XMOVNTQInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyMOVQMove QuadwordMoves a 64-bit value:••from an MMX register or 64-bit memory location to another MMX register, orfrom an MMX register to another MMX register or 64-bit memory location.The MOVQ instruction is an MMX™ instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionMOVQ mmx1, mmx2/mem640F 6F /rMoves 64-bit value from an MMX register or memorylocation to an MMX register.MOVQ mmx1/mem64, mmx20F 7F /rMoves 64-bit value from an MMX register to an MMXregister or memory location.mmx1mmx2/mem64063630copymmx1/mem6463mmx20630copymovq-64.epsRelated InstructionsMOVD, MOVDQA, MOVDQU, MOVDQ2Q, MOVQ2DQrFLAGS AffectedNoneInstruction ReferenceMOVQ37AMD64 Technology26569—Rev.
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