Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 6
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Compare rAX–rSP.PrefacexxiAMD64 Technology26569—Rev. 3.08—July 2007EBPExtended base pointer register.EFERExtended features enable register.eFLAGS16-bit or 32-bit flags register. Compare rFLAGS.EFLAGS32-bit (extended) flags register.eIP16-bit or 32-bit instruction-pointer register. Compare rIP.EIP32-bit (extended) instruction-pointer register.FLAGS16-bit flags register.GDTRGlobal descriptor table register.GPRsGeneral-purpose registers. For the 16-bit data size, these are AX, BX, CX, DX, DI, SI, BP, and SP.For the 32-bit data size, these are EAX, EBX, ECX, EDX, EDI, ESI, EBP, and ESP.
For the 64-bitdata size, these include RAX, RBX, RCX, RDX, RDI, RSI, RBP, RSP, and R8–R15.IDTRInterrupt descriptor table register.IP16-bit instruction-pointer register.LDTRLocal descriptor table register.MSRModel-specific register.r8–r15The 8-bit R8B–R15B registers, or the 16-bit R8W–R15W registers, or the 32-bit R8D–R15Dregisters, or the 64-bit R8–R15 registers.xxiiPreface26569—Rev. 3.08—July 2007AMD64 TechnologyrAX–rSPThe 16-bit AX, BX, CX, DX, DI, SI, BP, and SP registers, or the 32-bit EAX, EBX, ECX, EDX,EDI, ESI, EBP, and ESP registers, or the 64-bit RAX, RBX, RCX, RDX, RDI, RSI, RBP, and RSPregisters.
Replace the placeholder r with nothing for 16-bit size, “E” for 32-bit size, or “R” for 64bit size.RAX64-bit version of the EAX register.RBP64-bit version of the EBP register.RBX64-bit version of the EBX register.RCX64-bit version of the ECX register.RDI64-bit version of the EDI register.RDX64-bit version of the EDX register.rFLAGS16-bit, 32-bit, or 64-bit flags register.
Compare RFLAGS.RFLAGS64-bit flags register. Compare rFLAGS.rIP16-bit, 32-bit, or 64-bit instruction-pointer register. Compare RIP.RIP64-bit instruction-pointer register.RSI64-bit version of the ESI register.RSP64-bit version of the ESP register.SPStack pointer register.PrefacexxiiiAMD64 Technology26569—Rev. 3.08—July 2007SSStack segment register.TPRTask priority register (CR8), a new register introduced in the AMD64 architecture to speedinterrupt management.TRTask register.Endian OrderThe x86 and AMD64 architectures address memory using little-endian byte-ordering. Multibytevalues are stored with their least-significant byte at the lowest byte address, and they are illustratedwith their least significant byte at the right side. Strings are illustrated in reverse order, because theaddresses of their bytes increase from right to left.Related Documents••••••••••••••Peter Abel, IBM PC Assembly Language and Programming, Prentice-Hall, Englewood Cliffs, NJ,1995.Rakesh Agarwal, 80x86 Architecture & Programming: Volume II, Prentice-Hall, EnglewoodCliffs, NJ, 1991.AMD, AMD-K6™ MMX™ Enhanced Processor Multimedia Technology, Sunnyvale, CA, 2000.AMD, 3DNow!™ Technology Manual, Sunnyvale, CA, 2000.AMD, AMD Extensions to the 3DNow!™ and MMX™ Instruction Sets, Sunnyvale, CA, 2000.Don Anderson and Tom Shanley, Pentium Processor System Architecture, Addison-Wesley, NewYork, 1995.Nabajyoti Barkakati and Randall Hyde, Microsoft Macro Assembler Bible, Sams, Carmel, Indiana,1992.Barry B.
Brey, 8086/8088, 80286, 80386, and 80486 Assembly Language Programming,Macmillan Publishing Co., New York, 1994.Barry B. Brey, Programming the 80286, 80386, 80486, and Pentium Based Personal Computer,Prentice-Hall, Englewood Cliffs, NJ, 1995.Ralf Brown and Jim Kyle, PC Interrupts, Addison-Wesley, New York, 1994.Penn Brumm and Don Brumm, 80386/80486 Assembly Language Programming, WindcrestMcGraw-Hill, 1993.Geoff Chappell, DOS Internals, Addison-Wesley, New York, 1994.Chips and Technologies, Inc.
Super386 DX Programmer’s Reference Manual, Chips andTechnologies, Inc., San Jose, 1992.John Crawford and Patrick Gelsinger, Programming the 80386, Sybex, San Francisco, 1987.xxivPreface26569—Rev. 3.08—July 2007••••••••••••••••••••••AMD64 TechnologyCyrix Corporation, 5x86 Processor BIOS Writer's Guide, Cyrix Corporation, Richardson, TX,1995.Cyrix Corporation, M1 Processor Data Book, Cyrix Corporation, Richardson, TX, 1996.Cyrix Corporation, MX Processor MMX Extension Opcode Table, Cyrix Corporation, Richardson,TX, 1996.Cyrix Corporation, MX Processor Data Book, Cyrix Corporation, Richardson, TX, 1997.Ray Duncan, Extending DOS: A Programmer's Guide to Protected-Mode DOS, Addison Wesley,NY, 1991.William B. Giles, Assembly Language Programming for the Intel 80xxx Family, Macmillan, NewYork, 1991.Frank van Gilluwe, The Undocumented PC, Addison-Wesley, New York, 1994.John L.
Hennessy and David A. Patterson, Computer Architecture, Morgan Kaufmann Publishers,San Mateo, CA, 1996.Thom Hogan, The Programmer’s PC Sourcebook, Microsoft Press, Redmond, WA, 1991.Hal Katircioglu, Inside the 486, Pentium, and Pentium Pro, Peer-to-Peer Communications, MenloPark, CA, 1997.IBM Corporation, 486SLC Microprocessor Data Sheet, IBM Corporation, Essex Junction, VT,1993.IBM Corporation, 486SLC2 Microprocessor Data Sheet, IBM Corporation, Essex Junction, VT,1993.IBM Corporation, 80486DX2 Processor Floating Point Instructions, IBM Corporation, EssexJunction, VT, 1995.IBM Corporation, 80486DX2 Processor BIOS Writer's Guide, IBM Corporation, Essex Junction,VT, 1995.IBM Corporation, Blue Lightning 486DX2 Data Book, IBM Corporation, Essex Junction, VT,1994.Institute of Electrical and Electronics Engineers, IEEE Standard for Binary Floating-PointArithmetic, ANSI/IEEE Std 754-1985.Institute of Electrical and Electronics Engineers, IEEE Standard for Radix-Independent FloatingPoint Arithmetic, ANSI/IEEE Std 854-1987.Muhammad Ali Mazidi and Janice Gillispie Mazidi, 80X86 IBM PC and Compatible Computers,Prentice-Hall, Englewood Cliffs, NJ, 1997.Hans-Peter Messmer, The Indispensable Pentium Book, Addison-Wesley, New York, 1995.Karen Miller, An Assembly Language Introduction to Computer Architecture: Using the IntelPentium, Oxford University Press, New York, 1999.Stephen Morse, Eric Isaacson, and Douglas Albert, The 80386/387 Architecture, John Wiley &Sons, New York, 1987.NexGen Inc., Nx586 Processor Data Book, NexGen Inc., Milpitas, CA, 1993.PrefacexxvAMD64 Technology26569—Rev.
3.08—July 2007••NexGen Inc., Nx686 Processor Data Book, NexGen Inc., Milpitas, CA, 1994.Bipin Patwardhan, Introduction to the Streaming SIMD Extensions in the Pentium III,www.x86.org/articles/sse_pt1/ simd1.htm, June, 2000.•Peter Norton, Peter Aitken, and Richard Wilton, PC Programmer’s Bible, Microsoft Press,Redmond, WA, 1993.PharLap 386|ASM Reference Manual, Pharlap, Cambridge MA, 1993.PharLap TNT DOS-Extender Reference Manual, Pharlap, Cambridge MA, 1995.Sen-Cuo Ro and Sheau-Chuen Her, i386/i486 Advanced Programming, Van Nostrand Reinhold,New York, 1993.Jeffrey P. Royer, Introduction to Protected Mode Programming, course materials for an onsiteclass, 1992.Tom Shanley, Protected Mode System Architecture, Addison Wesley, NY, 1996.•••••••••SGS-Thomson Corporation, 80486DX Processor SMM Programming Manual, SGS-ThomsonCorporation, 1995.Walter A.
Triebel, The 80386DX Microprocessor, Prentice-Hall, Englewood Cliffs, NJ, 1992.John Wharton, The Complete x86, MicroDesign Resources, Sebastopol, California, 1994.Web sites and newsgroups:- www.amd.com- news.comp.arch- news.comp.lang.asm.x86- news.intel.microprocessors- news.microsoftxxviPreface26569—Rev. 3.08—July 20071AMD64 Technology64-Bit Media Instruction ReferenceThis chapter describes the function, mnemonic syntax, opcodes, affected flags, and possibleexceptions generated by the 64-bit media instructions.
These instructions operate on data located in the64-bit MMX registers. Most of the instructions operate in parallel on sets of packed elements calledvectors, although some operate on scalars. The instructions define both integer and floating-pointoperations, and include the legacy MMX™ instructions, the 3DNow!™ instructions, and the AMDextensions to the MMX and 3DNow! instruction sets.Each instruction that performs a vector (packed) operation is illustrated with a diagram. Figure 1-1 onpage 1 shows the conventions used in these diagrams. The particular diagram shows the PSLLW(packed shift left logical words) instruction.Arrowheads going to a source operandindicate the writing of the result. In thiscase, the result is written to the first sourceoperand, which is also the destination operand.First Source Operand(and Destination Operand)Second Source Operandmmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.shift leftshift leftOperation.
In this case,a bitwise shift-left.Arrowheads coming from a source operandindicate that the source operand providesa control function. In this case, the secondsource operand specifies the number of bitsto shift, and the first source operand specifiesthe data to be shifted.513-324.epsFile name ofthis figure (fordocumentationcontrol)Ellipses indicate that the operationis repeated for each element of thesource vectors. In this case, there are4 elements in each source vector, sothe operation is performed 4 times,in parallel.Figure 1-1. Diagram Conventions for 64-Bit Media InstructionsGray areas in diagrams indicate unmodified operand bits.Instruction Reference1AMD64 Technology26569—Rev.
3.08—July 2007Like the 128-bit media instructions, many of the 64-bit instructions independently and simultaneouslyperform a single operation on multiple elements of a vector and are thus classified as singleinstruction, multiple-data (SIMD) instructions.
A few 64-bit media instructions convert operands inMMX registers to operands in GPR, XMM, or x87 registers (or vice versa), or save or restore MMXstate, or reset x87state.Hardware support for a specific 64-bit media instruction depends on the presence of at least one of thefollowing CPUID functions:•••••MMX Instructions, indicated by bit 23 of CPUID function 0000_0001h and function 8000_0001h.AMD Extensions to MMX Instructions, indicated by bit 22 of CPUID function 8000_0001h.SSE, indicated by bit 25 of CPUID function 0000_0001h.SSE2, indicated by bit 26 of CPUID function 0000_0001h.AMD 3DNow! Instructions, indicated by bit 31 of CPUID function 8000_0001h.••AMD Extensions to 3DNow! Instructions, indicated by bit 30 of CPUID function 8000_0001h.FXSAVE and FXRSTOR, indicated by bit 24 of CPUID function 0000_0001h and function8000_0001h.The 64-bit media instructions can be used in legacy mode or long mode.
Their use in long mode isavailable if the following CPUID function is set:•Long Mode, indicated by bit 29 of CPUID function 8000_0001h.Compilation of 64-bit media programs for execution in 64-bit mode offers four primary advantages:access to the eight extended, 64-bit general-purpose registers (for a register set consisting ofGPR0–GPR15), access to the eight extended XMM registers (for a register set consisting ofXMM0–XMM15), access to the 64-bit virtual address space, and access to the RIP-relative addressingmode.For further information, see:••••2“64-Bit Media Programming” in Volume 1.“Summary of Registers and Data Types” in Volume 3.“Notation” in Volume 3.“Instruction Prefixes” in Volume 3.Instruction Reference26569—Rev.
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