Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 4
Текст из файла (страница 4)
. . . . . . . . . . . . . . . . . . . . . . 327FXTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329FYL2X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 331FYL2XP1. . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . 337ContentsvAMD64 Technologyvi26569—Rev. 3.08—July 2007Contents26569—Rev. 3.08—July 2007AMD64 TechnologyFiguresFigure 1-1.FiguresDiagram Conventions for 64-Bit Media Instructions . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 1viiAMD64 Technologyviii26569—Rev. 3.08—July 2007Figures26569—Rev. 3.08—July 2007AMD64 TechnologyTablesTable 1-1.Immediate-Byte Operand Encoding for 64-Bit PEXTRW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84Table 1-2.Numeric Range for PF2ID Results . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . 86Table 1-3.Numeric Range for PF2IW Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88Table 1-4.Numeric Range for PFACC Results . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . 91Table 1-5.Numeric Range for the PFADD Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93Table 1-6.Numeric Range for the PFCMPEQ Instruction . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . 96Table 1-7.Numeric Range for the PFCMPGE Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98Table 1-8.Numeric Range for the PFCMPGT Instruction . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . 101Table 1-9.Numeric Range for the PFMAX Instruction. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103Table 1-10.Numeric Range for the PFMIN Instruction . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105Table 1-11.Numeric Range for the PFMUL Instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107Table 1-12.Numeric Range of PFNACC Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . 109Table 1-13.Numeric Range of PFPNACC Result (Low Result). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112Table 1-14.Numeric Range of PFPNACC Result (High Result) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. 112Table 1-15.Numeric Range for the PFRCP Result . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115Table 1-16.Numeric Range for the PFRCP Result . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . 127Table 1-17.Numeric Range for the PFSUB Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130Table 1-18.Numeric Range for the PFSUBR Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
. . . . . . . . . . 132Table 1-19.Immediate-Byte Operand Encoding for 64-Bit PINSRW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137Table 1-20.Immediate-Byte Operand Encoding for PSHUFW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166Table 2-1.Storing Numbers as Integers . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258Table 2-2.Storing Numbers as Integers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261Table 2-3.Computing Arctangent of Numbers . . . . . . . . . . . . . . . . .
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 280TablesixAMD64 Technologyx26569—Rev. 3.08—July 2007Tables26569—Rev. 3.08—July 2007AMD64 TechnologyRevision HistoryDateRevisionDescriptionJuly 20073.08Added misaligned access support to applicable instructions.Deprecated 3DNow!™ instructions. Added AppendixA, ”Recommended Substitutions for 3DNow!™ Instructions,” onpage 335.Added minor clarifications and corrected typographical andformatting errors.September20063.07Added minor clarifications and corrected typographical andformatting errors.December20053.06Added minor clarifications and corrected typographical andformatting errors.December20043.05Added FISTTP instruction (SSE3).
Updated CPUID information inexception tables. Corrected several typographical and formattingerrors.September20033.04Clarified x87 condition codes for FPREM and FPREM1 instructions.Corrected tables of numeric ranges for results of PF2ID and PF2IWinstructions.3.03Corrected numerous typos and stylistic errors. Corrected descriptionof FYL2XP1 instruction. Clarified the description of the FXRSTORinstruction.April 2003Revision HistoryxiAMD64 Technologyxii26569—Rev. 3.08—July 2007Revision History26569—Rev.
3.08—July 2007AMD64 TechnologyPrefaceAbout This BookThis book is part of a multivolume work entitled the AMD64 Architecture Programmer’s Manual. Thistable lists each volume and its order number.TitleOrder No.Volume 1: Application Programming24592Volume 2: System Programming24593Volume 3: General-Purpose and System Instructions24594Volume 4: 128-Bit Media Instructions26568Volume 5: 64-Bit Media and x87 Floating-Point Instructions26569AudienceThis volume (Volume 5) is intended for all programmers writing application or system software for aprocessor that implements the x86-64 architecture.Contact InformationTo submit questions or comments concerning this document, contact our technical documentation staffat AMD64.Feedback@amd.com.OrganizationVolumes 3, 4, and 5 describe the AMD64 architecture’s instruction set in detail.
Together, they covereach instruction’s mnemonic syntax, opcodes, functions, affected flags, and possible exceptions.The AMD64 instruction set is divided into five subsets:•••••General-purpose instructionsSystem instructions128-bit media instructions64-bit media instructionsx87 floating-point instructionsSeveral instructions belong to—and are described identically in—multiple instruction subsets.PrefacexiiiAMD64 Technology26569—Rev. 3.08—July 2007This volume describes the 64-bit media and x87 floating-point instructions. The index at the end crossreferences topics within this volume.
For other topics relating to the AMD64 architecture, and forinformation on instructions in other subsets, see the tables of contents and indexes of the othervolumes.DefinitionsMany of the following definitions assume an in-depth knowledge of the legacy x86 architecture. See“Related Documents” on page xxiv for descriptions of the legacy x86 architecture.Terms and NotationIn addition to the notation described below, “Opcode-Syntax Notation” in Volume 3 describes notationrelating specifically to opcodes.1011bA binary value—in this example, a 4-bit value.F0EAhA hexadecimal value—in this example a 2-byte value.[1,2)A range that includes the left-most value (in this case, 1) but excludes the right-most value (in thiscase, 2).7–4A bit range, from bit 7 to 4, inclusive. The high-order bit is shown first.128-bit media instructionsInstructions that use the 128-bit XMM registers.
These are a combination of the SSE and SSE2instruction sets.64-bit media instructionsInstructions that use the 64-bit MMX registers. These are primarily a combination of MMX™ and3DNow!™ instruction sets, with some additional instructions from the SSE and SSE2 instructionsets.16-bit modeLegacy mode or compatibility mode in which a 16-bit address size is active.
See legacy mode andcompatibility mode.32-bit modeLegacy mode or compatibility mode in which a 32-bit address size is active. See legacy mode andcompatibility mode.xivPreface26569—Rev. 3.08—July 2007AMD64 Technology64-bit modeA submode of long mode. In 64-bit mode, the default address size is 64 bits and new features, suchas register extensions, are supported for system and application software.#GP(0)Notation indicating a general-protection exception (#GP) with error code of 0.absoluteSaid of a displacement that references the base of a code segment rather than an instruction pointer.Contrast with relative.ASIDAddress space identifier.biased exponentThe sum of a floating-point value’s exponent and a constant bias for a particular floating-point datatype. The bias makes the range of the biased exponent always positive, which allows reciprocationwithout overflow.byteEight bits.clearTo write a bit value of 0.
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