Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 12
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3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPADDB47AMD64 Technology26569—Rev.
3.08—July 2007PADDDPacked Add DoublewordsAdds each packed 32-bit integer value in the first source operand to the corresponding packed 32-bitinteger in the second source operand and writes the integer result of each addition in the correspondingdoubleword of the destination (first source). The first source/destination operand is an MMX registerand the second source operand is another MMX register or 64-bit memory location.The PADDD instruction operates on both signed and unsigned integers. If the result overflows, thecarry is ignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 32 bits ofeach result are written in the destination.The PADDD instruction is an MMX™ instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDD mmx1, mmx2/mem640F FE /rDescriptionAdds packed 32-bit integer values in an MMX registerand another MMX register or 64-bit memory location andwrites the result in the destination MMX register.mmx163mmx2/mem6432 3106332 310addaddpaddd-64.epsRelated InstructionsPADDB, PADDQ, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDWrFLAGS AffectedNone48PADDDInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPADDD49AMD64 Technology26569—Rev.
3.08—July 2007PADDQPacked Add QuadwordsAdds each packed 64-bit integer value in the first source operand to the corresponding packed 64-bitinteger in the second source operand and writes the integer result of each addition in the correspondingquadword of the destination (first source). The first source/destination operand is an MMX registerand the second source operand is another MMX register or 64-bit memory location.The PADDQ instruction operates on both signed and unsigned integers. If the result overflows, thecarry is ignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 64 bits ofeach result are written in the destination.The PADDQ instruction is an SSE2 instruction.
The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDQ mmx1, mmx2/mem640F D4 /rDescriptionAdds 64-bit integer value in an MMX register andanother MMX register or 64-bit memory location andwrites the result in the destination MMX register.mmx163mmx2/mem640630addpaddq-64.epsRelated InstructionsPADDB, PADDD, PADDSB, PADDSW, PADDUSB, PADDUSW, PADDWrFLAGS AffectedNone50PADDQInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPADDQ51AMD64 Technology26569—Rev.
3.08—July 2007PADDSBPacked Add Signed with Saturation BytesAdds each packed 8-bit signed integer value in the first source operand to the corresponding packed 8bit signed integer in the second source operand and writes the signed integer result of each addition inthe corresponding byte of the destination (first source). The first source/destination operand is anMMX register and the second source operand is another MMX register or 64-bit memory location.For each packed value in the destination, if the value is larger than the largest representable signed 8bit integer, it is saturated to 7Fh, and if the value is smaller than the smallest signed 8-bit integer, it issaturated to 80h.The PADDSB instruction is an MMX™ instruction.
The presence of this instruction set is indicated bya CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDSB mmx1, mmx2/mem640F EC /rDescriptionAdds packed byte signed integer values in an MMXregister and another MMX register or 64-bit memorylocation and writes the result in the destination MMXregister.mmx1....mmx2/mem64..630.....63.0......addaddsaturatesaturatepaddsb-64.epsRelated InstructionsPADDB, PADDD, PADDQ, PADDSW, PADDUSB, PADDUSW, PADDWrFLAGS AffectedNone52PADDSBInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPADDSB53AMD64 Technology26569—Rev.
3.08—July 2007PADDSWPacked Add Signed with Saturation WordsAdds each packed 16-bit signed integer value in the first source operand to the corresponding packed16-bit signed integer in the second source operand and writes the signed integer result of each additionin the corresponding word of the destination (first source). The first source/destination operand is anMMX register and the second source operand is another MMX register or 64-bit memory location.For each packed value in the destination, if the value is larger than the largest representable signed 16bit integer, it is saturated to 7FFFh, and if the value is smaller than the smallest signed 16-bit integer, itis saturated to 8000h.The PADDSW instruction is an MMX™ instruction.
The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePADDSW mmx1, mmx2/mem640F ED /rDescriptionAdds packed 16-bit signed integer values in an MMXregister and another MMX register or 64-bit memorylocation and writes the result in the destination MMXregister.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.addaddsaturatesaturatepaddsw-64.epsRelated InstructionsPADDB, PADDD, PADDQ, PADDSB, PADDUSB, PADDUSW, PADDWrFLAGS AffectedNone54PADDSWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPADDSW55AMD64 Technology26569—Rev.
3.08—July 2007PADDUSBPacked Add Unsigned with Saturation BytesAdds each packed 8-bit unsigned integer value in the first source operand to the corresponding packed8-bit unsigned integer in the second source operand and writes the unsigned integer result of eachaddition in the corresponding byte of the destination (first source). The first source/destination operandis an MMX register and the second source operand is another MMX register or 64-bit memorylocation.For each packed value in the destination, if the value is larger than the largest unsigned 8-bit integer, itis saturated to FFh, and if the value is smaller than the smallest unsigned 8-bit integer, it is saturated to00h.The PADDUSB instruction is an MMX™ instruction. The presence of this instruction set is indicatedby a CPUID feature bit.
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