Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 15
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The firstsource/destination operand is an MMX register and the second source operand is another MMXregister or 64-bit memory location.The PCMPEQW instruction is an MMX™ instruction. The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPEQW mmx1, mmx2/mem64DescriptionCompares packed 16-bit values in an MMX registerand an MMX register or 64-bit memory location.0F 75 /rmmx1..63 48 47 32 31 16 15.mmx2/mem64063 48 47 32 31 16 15..0.comparecompareall 1s or 0sall 1s or 0spcmpeqw-64.epsRelated InstructionsPCMPEQB, PCMPEQD, PCMPGTB, PCMPGTD, PCMPGTWrFLAGS AffectedNone76PCMPEQWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPCMPEQW77AMD64 Technology26569—Rev.
3.08—July 2007PCMPGTBPacked Compare Greater Than Signed BytesCompares corresponding packed signed bytes in the first and second source operands and writes theresult of each compare in the corresponding byte of the destination (first source). For each pair ofbytes, if the value in the first source operand is greater than the value in the second source operand, theresult is all 1s. If the value in the first source operand is less than or equal to the value in the secondsource operand, the result is all 0s. The first source/destination operand is an MMX register and thesecond source operand is another MMX register or 64-bit memory location.The PCMPGTB instruction is an MMX™ instruction. The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPGTB mmx1, mmx2/mem64DescriptionCompares packed signed bytes in an MMX registerand an MMX register or 64-bit memory location.0F 64 /rmmx163mmx2/mem64............0630......comparecompareall 1s or 0sall 1s or 0spcmpgtb-64.epsRelated InstructionsPCMPEQB, PCMPEQD, PCMPEQW, PCMPGTD, PCMPGTWrFLAGS AffectedNone78PCMPGTBInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPCMPGTB79AMD64 Technology26569—Rev.
3.08—July 2007PCMPGTDPacked Compare Greater Than SignedDoublewordsCompares corresponding packed signed 32-bit values in the first and second source operands andwrites the result of each compare in the corresponding 32 bits of the destination (first source). For eachpair of doublewords, if the value in the first source operand is greater than the value in the secondsource operand, the result is all 1s.
If the value in the first source operand is less than or equal to thevalue in the second source operand, the result is all 0s. The first source/destination operand is an MMXregister and the second source operand is another MMX register or 64-bit memory location.The PCMPGTD instruction is an MMX™ instruction. The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPGTD mmx1, mmx2/mem640F 66 /rDescriptionCompares packed signed 32-bit values in an MMXregister and an MMX register or 64-bit memorylocation.mmx163mmx2/mem6432 3106332 310compareall 1s or 0scompareall 1s or 0spcmpgtd-64.epsRelated InstructionsPCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTWrFLAGS AffectedNone80PCMPGTDInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPCMPGTD81AMD64 Technology26569—Rev.
3.08—July 2007PCMPGTWPacked Compare Greater Than Signed WordsCompares corresponding packed signed 16-bit values in the first and second source operands andwrites the result of each compare in the corresponding 16 bits of the destination (first source). For eachpair of words, if the value in the first source operand is greater than the value in the second sourceoperand, the result is all 1s. If the value in the first source operand is less than or equal to the value inthe second source operand, the result is all 0s.
The first source/destination operand is an MMX registerand the second source operand is another MMX register or 64-bit memory location.The PCMPGTW instruction is an MMX™ instruction. The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePCMPGTW mmx1, mmx2/mem64Description0F 65 /rCompares packed signed 16-bit values in an MMXregister and an MMX register or 64-bit memorylocation.mmx1....63 48 47 32 31 16 15mmx2/mem64063 48 47 32 31 16 15.0.comparecompareall 1s or 0sall 1s or 0spcmpgtw-64.epsRelated InstructionsPCMPEQB, PCMPEQD, PCMPEQW, PCMPGTB, PCMPGTDrFLAGS AffectedNone82PCMPGTWInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPCMPGTW83AMD64 Technology26569—Rev.
3.08—July 2007PEXTRWExtract Packed WordExtracts a 16-bit value from an MMX register, as selected by the immediate byte operand (as shown inTable 1-1) and writes it to the low-order word of a 32-bit general-purpose register, with zero-extensionto 32 bits.The PEXTRW instruction is a member of both the AMD MMX™ extensions and the SSE instructionset. The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume3.)MnemonicOpcodePEXTRW reg32, mmx, imm8DescriptionExtracts a 16-bit value from an MMX register andwrites it to low-order 16 bits of a general-purposeregister.0F C5 /r ibreg321531mmx063 48 47 32 31 16 1500imm87 0muxpextrw-64.epsTable 1-1.Immediate-Byte Operand Encoding for 64-Bit PEXTRWImmediate-ByteBit Field1–0Value of Bit FieldSource Bits Extracted015–0131–16247–32363–48Related InstructionsPINSRWrFLAGS AffectedNone84PEXTRWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to the MMX™ instruction set arenot supported, as indicated by EDX bit 22 of CPUIDfunction 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.x87 floating-pointexception pending, #MFXXXAn unmasked x87 floating-point exception waspending.Invalid opcode, #UDInstruction ReferencePEXTRW85AMD64 Technology26569—Rev. 3.08—July 2007PF2IDPacked Floating-Point to Integer DoublewordConversonConverts two packed single-precision floating-point values in an MMX register or a 64-bit memorylocation to two packed 32-bit signed integer values and writes the converted values in another MMXregister.
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