Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 17
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3.08—July 2007PFADDPacked Floating-Point AddAdds each packed single-precision floating-point value in the first source operand to thecorresponding packed single-precision floating-point value in the second operand and writes the resultof each addition in the corresponding doubleword of the destination (first source). The firstsource/destination operand is an MMX register. The second source operand is another MMX registeror 64-bit memory location. The numeric range for operands is shown in Table 1-5 on page 93.The PFADD instruction is an AMD 3DNow!™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionADDPSMnemonicOpcodePFADD mmx1, mmx2/mem64Description0F 0F /r9EAdds two packed single-precision floating-point values in anMMX register or 64-bit memory location and another MMXregister and writes each result in the destination MMXregister.mmx163mmx2/mem6432 3106332 310addaddpfadd.eps92PFADDInstruction Reference26569—Rev.
3.08—July 2007Table 1-5.AMD64 TechnologyNumeric Range for the PFADD ResultsMost-Significant DoublewordSource Operand00Source 1 andDestination+/–Normal01UnsupportedSource 2NormalSource 1Normal, +/– 0Unsupported3Source 1UndefinedSource 22UndefinedUndefinedNote:1. The sign of the result is the logical AND of the signs of the source operands.2. If the absolute value of the infinitely precise result is less than 2–126 (but not zero), the result is a zerowith the sign of the source operand that is larger in magnitude.
If the infinitely precise result is exactlyzero, the result is zero with the sign of source 1. If the absolute value of the infinitely precise result isgreater than or equal to 2128, the result is the largest normal number with the sign of source 1.3. “Unsupported” means that the exponent is all ones (1s).Instruction ReferencePFADD93AMD64 Technology26569—Rev. 3.08—July 2007Related InstructionsPFACC, PFNACC, PFPNACCrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC94XPFADDInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPFCMPEQPacked Floating-Point Compare EqualCompares each of the two packed single-precision floating-point values in the first source operandwith the corresponding packed single-precision floating-point value in the second source operand andwrites the result of each comparison in the corresponding doubleword of the destination (first source).For each pair of floating-point values, if the values are equal, the result is all 1s. If the values are notequal, the result is all 0s. The first source/destination operand is an MMX register. The second sourceoperand is another MMX register or 64-bit memory location. The numeric range for operands is shownin Table 1-6 on page 96.The PFCMPEQ instruction is an AMD 3DNow!™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts. For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionCMPSSMnemonicOpcodePFCMPEQ mmx1, mmx2/mem64Description0F 0F /r B0Compares two pairs of packed single-precision floatingpoint values in an MMX register and an MMX register or64-bit memory location.mmx16332 31mmx2/mem6406332 310comparecompareall 1s or 0sall 1s or 0spfcmpeq.epsInstruction ReferencePFCMPEQ95AMD64 TechnologyTable 1-6.26569—Rev.
3.08—July 2007Numeric Range for the PFCMPEQ InstructionSource 2OperandSource 1 andDestinationValue0NormalUnsupported0FFFF_FFFFh10000_0000h0000_0000h0000_0000h0000_0000h orFFFF_FFFFh20000_0000h0000_0000h0000_0000hUndefinedNormalUnsupported3Note:1. Positive zero is equal to negative zero.2. The result is FFFF_FFFFh if source 1 and source 2 have identical signs, exponents, and mantissas.Otherwise, the result is 0000_0000h.3. “Unsupported” means that the exponent is all ones (1s).Related InstructionsPFCMPGE, PFCMPGTrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC96XPFCMPEQInstruction Reference26569—Rev.
3.08—July 2007PFCMPGEAMD64 TechnologyPacked Floating-Point Compare Greater or EqualCompares each of the two packed single-precision floating-point values in the first source operandwith the corresponding packed single-precision floating-point value in the second source operand andwrites the result of each comparison in the corresponding doubleword of the destination (first source).For each pair of floating-point values, if the value in the first source operand is greater than or equal tothe value in the second source operand, the result is all 1s.
If the value in the first source operand is lessthan the value in the second source operand, the result is all 0s. The first source/destination operand isan MMX register. The second source operand is another MMX register or 64-bit memory location. Thenumeric range for operands is shown in Table 1-7 on page 98.The PFCMPGE instruction is a 3DNow!™ instruction. The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts.
For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionCMPPSMnemonicOpcodePFCMPGE mmx1,mmx2/mem64DescriptionCompares two pairs of packed single-precision floatingpoint values in an MMX register and an MMX register or64-bit memory location.0F 0F /r 90mmx16332 31mmx2/mem6406332 310comparecompareall 1s or 0sall 1s or 0spfcmpge.epsInstruction ReferencePFCMPGE97AMD64 TechnologyTable 1-7.26569—Rev. 3.08—July 2007Numeric Range for the PFCMPGE InstructionSource 2OperandValue0NormalUnsupportedFFFF_FFFFh10000_0000h,FFFF_FFFFh2UndefinedNormal0000_0000h,FFFF_FFFFh30000_0000h,FFFF_FFFFh4UndefinedUnsupported5UndefinedUndefinedUndefined0Source 1 andDestinationNote:1.2.3.4.Positive zero is equal to negative zero.The result is FFFF_FFFFh, if source 2 is negative.
Otherwise, the result is 0000_0000h.The result is FFFF_FFFFh, if source 1 is positive. Otherwise, the result is 0000_0000h.The result is FFFF_FFFFh, if source 1 is positive and source 2 is negative, or if they are both negativeand source 1 is smaller than or equal in magnitude to source 2, or if source 1 and source 2 are bothpositive and source 1 is greater than or equal in magnitude to source 2. The result is 0000_0000h in allother cases.5. “Unsupported” means that the exponent is all ones (1s).Related InstructionsPFCMPEQ, PFCMPGTrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD 3DNow!™ instructions are not supported,as indicated by EDX bit 31 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XA page fault resulted from the execution of theinstruction.Invalid opcode, #UDGeneral protection, #GPPage fault, #PF98XPFCMPGEInstruction Reference26569—Rev.
3.08—July 2007ExceptionRealx87 floating-pointexception pending, #MFXAlignment check, #ACInstruction ReferenceAMD64 TechnologyVirtual8086 ProtectedCause of ExceptionXXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.PFCMPGE99AMD64 TechnologyPFCMPGT26569—Rev. 3.08—July 2007Packed Floating-Point Compare Greater ThanCompares each of the two packed single-precision floating-point values in the first source operandwith the corresponding packed single-precision floating-point value in the second source operand andwrites the result of each comparison in the corresponding doubleword of the destination (first source).For each pair of floating-point values, if the value in the first source operand is greater than the value inthe second source operand, the result is all 1s. If the value in the first source operand is less than orequal to the value in the second source operand, the result is all 0s.
The first source/destination operandis an MMX register. The second source operand is another MMX register or 64-bit memory location.The numeric range for operands is shown in Table 1-8 on page 101.The PFCMPGT instruction is an AMD 3DNow!™ instruction. The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)AMD no longer recommends the use of 3DNow! instructions, which have been superceded by theirmore efficient 128-bit media counterparts.
For a complete list of recommended instructionsubstitutions, see Appendix A, “Recommended Substitutions for 3DNow!™ Instructions” onpage 335.Recommended Instruction SubstitutionCMPPSMnemonicOpcodePFCMPGT mmx1,mmx2/mem64DescriptionCompares two pairs of packed single-precision floatingpoint values in an MMX register and an MMX register or64-bit memory location.0F 0F /r A0mmx16332 31mmx2/mem6406332 310comparecompareall 1s or 0sall 1s or 0spfcmpgt.eps100PFCMPGTInstruction Reference26569—Rev. 3.08—July 2007Table 1-8.AMD64 TechnologyNumeric Range for the PFCMPGT InstructionSource 2OperandValue0NormalUnsupported0000_0000h0000_0000h,FFFF_FFFFh1UndefinedNormal0000_0000h,FFFF_FFFFh20000_0000h,FFFF_FFFFh3UndefinedUnsupported4UndefinedUndefinedUndefined0Source 1 andDestinationNote:1. The result is FFFF_FFFFh, if source 2 is negative. Otherwise, the result is 0000_0000h.2.
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