Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 23
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Immediate-Byte Operand Encoding for 64-Bit PINSRWImmediate-ByteBit Field1–0Value of Bit FieldDestination Bits Filled015–0131–16247–32363–48Related InstructionsPEXTRWrFLAGS AffectedNoneInstruction ReferencePINSRW137AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to the MMX™ instruction set arenot supported, as indicated by EDX bit 22 of CPUIDfunction 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC138XPINSRWInstruction Reference26569—Rev.
3.08—July 2007PMADDWDAMD64 TechnologyPacked Multiply Words and Add DoublewordsMultiplies each packed 16-bit signed value in the first source operand by the corresponding packed 16bit signed value in the second source operand, adds the adjacent intermediate 32-bit results of eachmultiplication (for example, the multiplication results for the adjacent bit fields 63–48 and 47–32, and31–16 and 15–0), and writes the 32-bit result of each addition in the corresponding doubleword of thedestination (first source). The first source/destination operand is an MMX register and the secondsource operand is another MMX register or 64-bit memory location.If all four of the 16-bit source operands used to produce a 32-bit multiply-add result have the value8000h, the 32-bit result is 8000_0000h, which is not the correct 32-bit signed result.The PMADDWD instruction is an MMX™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePMADDWD mmx1, mmx2/mem64DescriptionMultiplies four packed 16-bit signed values in anMMX register and another MMX register or 64-bitmemory location, adds intermediate results, andwrites the result in the destination MMX register.0F F5 /rmmx163 48 47 32 31 16 15mmx2/mem64063 48 47 32 31 16 150multiplymultiplyaddmultiplymultiplyadd6332 310pmaddwd-64.epsRelated InstructionsPMULHUW, PMULHW, PMULLW, PMULUDQrFLAGS AffectedNoneInstruction ReferencePMADDWD139AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC140XPMADDWDInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPMAXSWPacked Maximum Signed WordsCompares each of the packed 16-bit signed integer values in the first source operand with thecorresponding packed 16-bit signed integer value in the second source operand and writes themaximum of the two values for each comparison in the corresponding word of the destination (firstsource). The first source/destination and second source operands are an MMX register and an MMXregister or 64-bit memory location.The PMAXSW instruction is an AMD extension to MMX™ instruction set and is an SSE instruction.The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePMAXSW mmx1, mmx2/mem640F EE /rDescriptionCompares packed signed 16-bit integer values in an MMXregister and another MMX register or 64-bit memorylocation and writes the maximum value of each comparein destination MMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.maximummaximumpmaxsw-64.epsRelated InstructionsPMAXUB, PMINSW, PMINUBrFLAGS AffectedNoneInstruction ReferencePMAXSW141AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to MMX are not supported, asindicated by EDX bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC142XPMAXSWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPMAXUBPacked Maximum Unsigned BytesCompares each of the packed 8-bit unsigned integer values in the first source operand with thecorresponding packed 8-bit unsigned integer value in the second source operand and writes themaximum of the two values for each comparison in the corresponding byte of the destination (firstsource). The first source/destination and second source operands are an MMX register and an MMXregister or 64-bit memory location.The PMAXUB instruction is an AMD extension to MMX™ instruction set and is an SSE instruction.The presence of this instruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePMAXUB mmx1, mmx2/mem640F DE /rDescriptionCompares packed unsigned 8-bit integer values in anMMX register and another MMX register or 64-bitmemory location and writes the maximum value of eachcompare in the destination MMX register.mmx1....mmx2/mem64..630.....63.0......maximummaximumpmaxub-64.epsRelated InstructionsPMAXSW, PMINSW, PMINUBrFLAGS AffectedNoneInstruction ReferencePMAXUB143AMD64 Technology26569—Rev.
3.08—July 2007ExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to MMX are not supported, asindicated by EDX bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #AC144XPMAXUBInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyPMINSWPacked Minimum Signed WordsCompares each of the packed 16-bit signed integer values in the first source operand with thecorresponding packed 16-bit signed integer value in the second source operand and writes theminimum of the two values for each comparison in the corresponding word of the destination (firstsource). The first source/destination and second source operands are an MMX register and an MMXregister or 64-bit memory location.The PMINSW instruction is an AMD extension to MMX™ instruction set and is an SSE instruction.The presence of this instruction set is indicated by CPUID feature bits.
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