Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 27
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(See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRAD mmx1, mmx2/mem640F E2 /rRight-shifts packed doublewords in an MMX registerby the amount specified in an MMX register or 64-bitmemory location.PSRAD mmx, imm80F 72 /4 ibRight-shifts packed doublewords in an MMX registerby the amount specified in an immediate byte value.mmx16332 31mmx2/mem646300shift rightshift rightmmx63imm832 317 00shift rightshift rightpsrad-64.eps174PSRADInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyRelated InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSRAD175AMD64 Technology26569—Rev.
3.08—July 2007PSRAWPacked Shift Right Arithmetic WordsRight-shifts each of the packed 16-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding word of thedestination (first source). The first source/destination and second source operands are:••an MMX register and another MMX register or 64-bit memory location, oran MMX register and an immediate byte value.The high-order bits that are emptied by the shift operation are filled with the sign bit of the word’sinitial value.
If the shift value is greater than 15, each word in the destination is filled with the sign bitof the word’s initial value.The PSRAW instruction is an MMX™ instruction. The presence of this instruction set is indicated byCPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRAW mmx1, mmx2/mem640F E1 /rRight-shifts packed words in an MMX register by theamount specified in an MMX register or 64-bitmemory location.PSRAW mmx, imm80F 71 /4 ibRight-shifts packed words in an MMX register by theamount specified in an immediate byte value.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063.shift rightarithmeticshift rightarithmeticmmx.imm8.63 48 47 32 31 16 15.shift rightarithmetic07 00.shift rightarithmeticpsraw-64.eps176PSRAWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyRelated InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRLD, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSRAW177AMD64 Technology26569—Rev.
3.08—July 2007PSRLDPacked Shift Right Logical DoublewordsRight-shifts each of the packed 32-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding doubleword of thedestination (first source). The first source/destination and second source operands are:••an MMX register and another MMX register or 64-bit memory location, oran MMX register and an immediate byte value.The high-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greaterthan 31, the destination is cleared to 0.The PSRLD instruction is an MMX™ instruction.
The presence of this instruction set is indicated byCPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRLD mmx1, mmx2/mem640F D2 /rRight-shifts packed doublewords in an MMX registerby the amount specified in an MMX register or 64-bitmemory location.PSRLD mmx, imm80F 72 /2 ibRight-shifts packed doublewords in an MMX registerby the amount specified in an immediate byte value.mmx16332 31mmx2/mem646300shift rightshift rightmmx63imm832 317 00shift rightshift rightpsrld-64.eps178PSRLDInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyRelated InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSRLD179AMD64 Technology26569—Rev.
3.08—July 2007PSRLQPacked Shift Right Logical QuadwordsRight-shifts each 64-bit value in the first source operand by the number of bits specified in the secondsource operand and writes each shifted value in the corresponding quadword of the destination (firstsource). The first source/destination and second source operands are:••an MMX register and another MMX register or 64-bit memory location, oran MMX register and an immediate byte value.The high-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greaterthan 63, the destination is cleared to 0.The PSRLQ instruction is an MMX™ instruction.
The presence of this instruction set is indicated byCPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRLQ mmx1, mmx2/mem640F D3 /rRight-shifts quadword in an MMX register by theamount specified in an MMX register or 64-bit memorylocation.PSRLQ mmx, imm80F 73 /2 ibRight-shifts quadword in an MMX register by theamount specified in an immediate byte value.mmx163mmx2/mem640630shift rightmmx63imm87 00shift rightpsrlq-64.epsRelated InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLW180PSRLQInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSRLQ181AMD64 Technology26569—Rev.
3.08—July 2007PSRLWPacked Shift Right Logical WordsRight-shifts each of the packed 16-bit values in the first source operand by the number of bits specifiedin the second operand and writes each shifted value in the corresponding word of the destination (firstsource). The first source/destination and second source operands are:••an MMX register and another MMX register or 64-bit memory location, oran MMX register and an immediate byte value.The high-order bits that are emptied by the shift operation are cleared to 0.
If the shift value is greaterthan 15, the destination is cleared to 0.The PSRLW instruction is an MMX™ instruction. The presence of this instruction set is indicated byCPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRLW mmx1, mmx2/mem640F D1 /rRight-shifts packed words in an MMX register by theamount specified in an MMX register or 64-bitmemory location.PSRLW mmx, imm80F 71 /2 ibRight-shifts packed words in an MMX register by theamount specified in an immediate byte value.mmx1.mmx2/mem64.63 48 47 32 31 16 15.0630.shift rightshift rightmmx.imm8.63 48 47 32 31 16 15.7 00.shift rightshift rightpsrlw-64.eps182PSRLWInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyRelated InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSRLW183AMD64 Technology26569—Rev.
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