Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 26
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3.08—July 2007Table 1-20. Immediate-Byte Operand Encoding for PSHUFWDestination Bits FilledImmediate-ByteBit Field15–031–1647–3263–481–03–25–47–6Value of Bit FieldSource Bits Moved015–0131–16247–32363–48015–0131–16247–32363–48015–0131–16247–32363–48015–0131–16247–32363–48Related InstructionsPSHUFD, PSHUFHW, PSHUFLWrFLAGS AffectedNone166PSHUFWInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealXVirtual8086 ProtectedXCause of ExceptionXThe emulate bit (EM) of CR0 was set to 1.XXXThe SSE instructions are not supported, as indicatedby EDX bit 25 in CPUID function 0000_0001h; andthe AMD extensions to MMX are not supported, asindicated by EDX bit 22 of CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSHUFW167AMD64 Technology26569—Rev.
3.08—July 2007PSLLDPacked Shift Left Logical DoublewordsLeft-shifts each of the packed 32-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding doubleword of thedestination (first source). The first source/destination and second source operands are:••an MMX register and another MMX register or 64-bit memory location, oran MMX register and an immediate byte value.The low-order bits that are emptied by the shift operation are cleared to 0.
If the shift value is greaterthan 31, the destination is cleared to all 0s.The PSLLD instruction is an MMX™ instruction. The presence of this instruction set is indicated byCPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSLLD mmx1, mmx2/mem640F F2 /rLeft-shifts packed doublewords in an MMX registerby the amount specified in an MMX register or 64-bitmemory location.PSLLD mmx, imm80F 72 /6 ibLeft-shifts packed doublewords in an MMX registerby the amount specified in an immediate byte value.mmx163mmx2/mem6432 310630shift leftshift leftmmx63imm832 317 00shift leftshift leftpslld-64.epsRelated InstructionsPSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW168PSLLDInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSLLD169AMD64 Technology26569—Rev.
3.08—July 2007PSLLQPacked Shift Left Logical QuadwordsLeft-shifts each 64-bit value in the first source operand by the number of bits specified in the secondsource operand and writes each shifted value in the corresponding quadword of the destination (firstsource). The first source/destination and second source operands are:••an MMX register and another MMX register or 64-bit memory location, oran MMX register and an immediate byte value.The low-order bits that are emptied by the shift operation are cleared to 0.
If the shift value is greaterthan 63, the destination is cleared to all 0s.The PSLLQ instruction is an MMX™ instruction. The presence of this instruction set is indicated byCPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSLLQ mmx1, mmx2/mem640F F3 /rLeft-shifts quadword in an MMX register by theamount specified in an MMX register or 64-bitmemory location.PSLLQ mmx, imm80F 73 /6 ibLeft-shifts quadword in an MMX register by theamount specified in an immediate byte value.mmx163mmx2/mem640630shift leftmmx63imm87 00shift leftpsllq-64.epsRelated InstructionsPSLLD, PSLLDQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLWrFLAGS AffectedNone170PSLLQInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSLLQ171AMD64 Technology26569—Rev.
3.08—July 2007PSLLWPacked Shift Left Logical WordsLeft-shifts each of the packed 16-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding word of thedestination (first source). The first source/destination and second source operands are:••an MMX register and another MMX register or 64-bit memory location, oran MMX register and an immediate byte value.The low-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greaterthan 15, the destination is cleared to all 0s.The PSLLW instruction is an MMX™ instruction. The presence of this instruction set is indicated byCPUID feature bits.
(See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSLLW mmx1, mmx2/mem640F F1 /rLeft-shifts packed words in an MMX register by theamount specified in an MMX register or 64-bitmemory location.PSLLW mmx, imm80F 71 /6 ibLeft-shifts packed words in an MMX register by theamount specified in an immediate byte value.mmx1.mmx2/mem64.63 48 47 32 31 16 15.0630.shift leftshift leftmmx.imm8.63 48 47 32 31 16 15.7 00.shift leftshift leftpsllw-64.epsRelated InstructionsPSLLD, PSLLDQ, PSLLQ, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQ, PSRLW172PSLLWInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyrFLAGS AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSLLW173AMD64 Technology26569—Rev.
3.08—July 2007PSRADPacked Shift Right Arithmetic DoublewordsRight-shifts each of the packed 32-bit values in the first source operand by the number of bits specifiedin the second source operand and writes each shifted value in the corresponding doubleword of thedestination (first source). The first source/destination and second source operands are:••an MMX register and another MMX register or 64-bit memory location, oran MMX register and an immediate byte value.The high-order bits that are emptied by the shift operation are filled with the sign bit of thedoubleword’s initial value. If the shift value is greater than 31, each doubleword in the destination isfilled with the sign bit of the doubleword’s initial value.The PSRAD instruction is an MMX™ instruction. The presence of this instruction set is indicated byCPUID feature bits.
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