Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 29
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The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePSUBUSB mmx1, mmx2/mem640F D8 /rDescriptionSubtracts packed byte unsigned integer values in anMMX register or 64-bit memory location from packedbyte integer values in another MMX register andwrites the result in the destination MMX register.mmx163mmx2/mem64............0630......subtractsaturatesubtractsaturatepsubusb-64.epsRelated InstructionsPSUBB, PSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSW, PSUBWrFLAGS AffectedNone194PSUBUSBInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSUBUSB195AMD64 Technology26569—Rev.
3.08—July 2007PSUBUSWPacked Subtract Unsigned and Saturate WordsSubtracts each packed 16-bit unsigned integer value in the second source operand from thecorresponding packed 16-bit unsigned integer in the first source operand and writes the unsignedinteger result of each subtraction in the corresponding word of the destination (first source). The firstsource/destination operand is an MMX register and the second source operand is another MMXregister or 64-bit memory location.For each packed value in the destination, if the value is larger than the largest unsigned 16-bit integer,it is saturated to FFFFh, and if the value is smaller than the smallest unsigned 16-bit integer, it issaturated to 0000h.The PSUBUSW instruction is an MMX™ instruction.
The presence of this instruction set is indicatedby CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePSUBUSW mmx1, mmx2/mem640F D9 /rDescriptionSubtracts packed 16-bit unsigned integer values inan MMX register or 64-bit memory location frompacked 16-bit integer values in another MMX registerand writes the result in the destination MMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.subtractsaturatesubtractsaturatepsubusw-64.epsRelated InstructionsPSUBB, PSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBWrFLAGS AffectedNone196PSUBUSWInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSUBUSW197AMD64 Technology26569—Rev.
3.08—July 2007PSUBWPacked Subtract WordsSubtracts each packed 16-bit integer value in the second source operand from the correspondingpacked 16-bit integer in the first source operand and writes the integer result of each subtraction in thecorresponding word of the destination (first source). The first source/destination operand is an MMXregister and the second source operand is another MMX register or 64-bit memory location.This instruction operates on both signed and unsigned integers.
If the result overflows, the carry isignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 16 bits of theresult are written in the destination.The PSUBW instruction is an MMX™ instruction. The presence of this instruction set is indicated byCPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePSUBW mmx1, mmx2/mem640F F9 /rDescriptionSubtracts packed 16-bit integer values in an MMXregister or 64-bit memory location from packed 16-bitinteger values in another MMX register and writes theresult in the destination MMX register.mmx1.mmx2/mem64.63 48 47 32 31 16 15.063 48 47 32 31 16 15..0.subtractsubtractpsubw-64.epsRelated InstructionsPSUBB, PSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBUSWrFLAGS AffectedNone198PSUBWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSUBW199AMD64 Technology26569—Rev.
3.08—July 2007PSWAPDPacked Swap DoublewordSwaps (reverses) the two packed 32-bit values in the source operand and writes each swapped value inthe corresponding doubleword of the destination. The source operand is an MMX register or 64-bitmemory location. The destination is another MMX register.The PSWAPD instruction is an extension to the AMD 3DNow!™ instruction set. The presence of thisinstruction set is indicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePSWAPD mmx1, mmx2/mem64Description0F 0F /r BBSwaps packed 32-bit values in an MMX register or 64bit memory location and writes each value in thedestination MMX register.mmx16332 31mmx2/mem6406332 31copy6332 3100copypswapd.epsRelated InstructionsNonerFLAGS AffectedNone200PSWAPDInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe AMD Extensions to 3DNow!™ are not supported,as indicated by EDX bit 30 in CPUID function8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPSWAPD201AMD64 Technology26569—Rev.
3.08—July 2007PUNPCKHBWUnpack and Interleave High BytesUnpacks the high-order bytes from the first and second source operands and packs them intointerleaved-byte words in the destination (first source). The low-order bytes of the source operands areignored. The first source/destination operand is an MMX register and the second source operand isanother MMX register or 64-bit memory location.If the second source operand is all 0s, the destination contains the bytes from the first source operandzero-extended to 16 bits. This operation is useful for expanding unsigned 8-bit values to unsigned 16bit operands for subsequent processing that requires higher precision.The PUNPCKHBW instruction is an MMX™ instruction.
The presence of this instruction set isindicated by CPUID feature bits. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKHBW mmx1,mmx2/mem64DescriptionUnpacks the four high-order bytes in an MMX registerand another MMX register or 64-bit memory locationand packs them into interleaved bytes in thedestination MMX register.0F 68 /rmmx163mmx2/mem6432 31.063.copy32 31.copycopy.63. .0.copy.32 310punpckhbw-64.epsRelated InstructionsP U N P C K H D Q , P U N P C K H Q D Q , P U N P C K H W D , P U N P C K L B W, P U N P C K L D Q ,PUNPCKLQDQ, PUNPCKLWDrFLAGS AffectedNone202PUNPCKHBWInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe emulate bit (EM) of CR0 was set to 1.XXXThe MMX™ instructions are not supported, asindicated by EDX bit 23 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXA page fault resulted from the execution of theinstruction.XXAn unmasked x87 floating-point exception waspending.XXAn unaligned memory reference was performed whilealignment checking was enabled.Invalid opcode, #UDGeneral protection, #GPPage fault, #PFx87 floating-pointexception pending, #MFAlignment check, #ACInstruction ReferenceXPUNPCKHBW203AMD64 Technology26569—Rev.
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