Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 33
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Then, if theexception is masked (IM bit set to 1 in the x87 control word), the instruction sets the flags to“unordered.” If the exception is unmasked (IM bit cleared to 0), the instruction does not set the flags.The FUCOMIx instructions perform the same operations as the FCOMIx instructions, but do not setthe IE bit for QNaNs.Support for the FCOMIx instruction is indicated by EDX bit 0 (FPU) and EDX bit 15 (CMOV) asreturned by either CPUID function 0000_0001h or CPUID function 8000_0001h.MnemonicOpcodeDescriptionFCOMI ST(0),ST(i)DB F0+iCompare the contents of ST(0) with the contents of ST(i)and set status flags to reflect the results of the comparison.FCOMIP ST(0),ST(i)DF F0+iCompare the contents of ST(0) with the contents of ST(i),set status flags to reflect the results of the comparison, andpop the x87 register stack.Related InstructionsFCOM, FCOMPP, FICOM, FICOMP, FTST, FUCOMI, FUCOMIP, FXAMrFLAGS AffectedZFPFCF000ST(0) > source001ST(0) < source100ST(0) = source111Operands were unorderedInstruction ReferenceCompare ResultFCOMIx237AMD64 Technology26569—Rev.
3.08—July 2007x87 Condition Codex87 Condition CodeValueDescriptionC0C10x87 stack underflow, if an x87 register stack fault was detected.C2C3Note: A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionInvalid opcode, #UDXXXThe conditional move instructions are not supported, asindicated by EDX bit 0 and EDX bit 15 in CPUID function0000_0001h or function 8000_0001h.Device not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE)XXXA source operand was an SNaN value, a QNaN value, oran unsupported format.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.238FCOMIxInstruction Reference26569—Rev.
3.08—July 2007AMD64 TechnologyFCOSFloating-Point CosineComputes the cosine of the radian value in ST(0) and stores the result in ST(0).If the radian value lies outside the valid range of –263 to +263 radians, the instruction sets the C2 flag inthe x87 status word to 1 to indicate the value is out of range and does not change the value in ST(0).MnemonicFCOSOpcodeDescriptionD9 FFReplace ST(0) with the cosine of ST(0).Related InstructionsFPTAN, FPATAN, FSIN, FSINCOSrFLAGS AffectedNonex87 Condition Codex87 Condition CodeValueC0UDescription0No precision exception occurred.0x87 stack underflow, if an x87 register stack fault was detected.0Result was rounded down, if a precision exception was detected.1Result was rounded up, if a precision exception was detected.0Source operand was in range.1Source operand was out of range.C1C2C3UNote: A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags are blank. Undefined flags are U.Instruction ReferenceFCOS239AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) is set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE)XXXA source operand was an SNaN value or an unsupportedformat.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.Underflow exception(UE)XXXA rounded result was too small to fit into the format of thedestination operand.Precision exception(PE)XXXA result could not be represented exactly in the destinationformat.240FCOSInstruction Reference26569—Rev.
3.08—July 2007FDECSTPAMD64 TechnologyFloating-Point Decrement Stack-Top PointerDecrements the top-of-stack pointer (TOP) field of the x87 status word. If the TOP field contains 0, itis set to 7. In other words, this instruction rotates the stack by one position.MnemonicOpcodeFDECSTPD9 F6DescriptionDecrement the TOP field in the x87 status word.Before FDECSTPAfter FDECSTPData RegisterValueStack PointerStack PointerValue7num1ST(7)ST(0)num16num2ST(6)ST(7)num25num3ST(5)ST(6)num34num4ST(4)ST(5)num43num5ST(3)ST(4)num52num6ST(2)ST(3)num61num7ST(1)ST(2)num70num8ST(0)ST(1)num8Related InstructionsFINCSTPrFLAGS AffectedNonex87 Condition Codex87 Condition CodeValueC0UC10C2UC3UDescriptionNote: A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags are blank. Undefined flags are U.Instruction ReferenceFDECSTP241AMD64 Technology26569—Rev. 3.08—July 2007ExceptionsVirtual8086 ProtectedExceptionRealDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.242Cause of ExceptionFDECSTPInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyFDIVFDIVPFIDIVFloating-Point DivideDivides the value in a floating-point register by the value in another register or a memory location andstores the result in the register containing the dividend.
For the FDIV and FDIVP instructions, thedivisor value in memory can be stored in single-precision or double-precision floating-point format.If only one operand is specified, the instruction divides the value in ST(0) by the value in the specifiedmemory location.If no operands are specified, the FDIVP instruction divides the value in ST(1) by the value in ST(0),stores the result in ST(1), and pops the x87 register stack.The FIDIV instruction converts a divisor in word integer or short integer format to double-extendedprecision floating-point format before performing the division.
It treats an integer 0 as +0.If the zero-divide exception is not masked (ZM bit cleared to 0 in the x87 control word) and theoperation causes a zero-divide exception (sets the ZE bit in the x87 status word to 1), the operationstores no result. If the zero-divide exception is masked (ZM bit set to 1), a zero-divide exceptioncauses ±∞ to be stored.The sign of the operands, even if one of the operands is 0, determines the sign of the result.MnemonicOpcodeDescriptionFDIV ST(0),ST(i)D8 F0+iReplace ST(0) with ST(0)/ST(i).FDIV ST(i),ST(0)DC F8+iReplace ST(i) with ST(i)/ST(0).FDIV mem32realD8 /6Replace ST(0) with ST(0)/mem32real.FDIV mem64realDC /6Replace ST(0) with ST(0)/mem64real.FDIVPDE F9Replace ST(1) with ST(1)/ST(0), and pop the x87 registerstack.FDIVP ST(i),ST(0)DE F8+iReplace ST(i) with ST(i)/ST(0), and pop the x87 registerstack.FIDIV mem16intDE /6Replace ST(0) with ST(0)/mem16int.FIDIV mem32intDA /6Replace ST(0) with ST(0)/mem32int.Related InstructionsFDIVR, FDIVRP, FIDIVRrFLAGS AffectedNoneInstruction ReferenceFDIVx243AMD64 Technology26569—Rev.
3.08—July 2007x87 Condition Codex87 Condition CodeValueC0UDescription0No precision exception occurred.0x87 stack underflow, if an x87 register stack fault was detected.0Result was rounded down, if a precision exception was detected.1Result was rounded up, if a precision exception was detected.C1C2UC3UNote: A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit orwas non-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or wasnon-canonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXAn unmasked x87 floating-point exception was pending.x87 floating-pointexception pending,#MFXx87 Floating-Point Exception Generated, #MFXXXA source operand was an SNaN value or an unsupportedformat.XXX±infinity was divided by ±infinity.XXX±zero was divided by ±zero.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.Zero-divideexception (ZE)XXXA non-zero value was divided by ±zero.Invalid-operationexception (IE)244FDIVxInstruction Reference26569—Rev.
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