Volume 5 64-Bit Media and x87 Floating-Point Instructions (794099), страница 37
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Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE) withstack fault (SF)XInstruction ReferenceXXAn x87 stack overflow occurred.FLDLN2273AMD64 Technology26569—Rev. 3.08—July 2007FLDPIFloating-Point Load PiPushes π onto the x87 register stack. The value in ST(0) is the result, in double-extended-precisionformat, of rounding an internal 66-bit constant according to the setting of the RC field in the x87control word register.MnemonicOpcodeFLDPIDescriptionPush π onto the x87 register stack.D9 EBRelated InstructionsFLD, FLD1, FLDZ, FLDL2T, FLDL2E, FLDLG2, FLDLN2rFLAGS AffectedNonex87 Condition Codex87 Condition CodeValueC0UDescription0No x87 stack fault occurred.1x87 stack overflow, if an x87 register stack fault was detected.C1C2UC3UNote: A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE) withstack fault (SF)274XXXAn x87 stack overflow occurred.FLDPIInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyFLDZFloating-Point Load +0.0Pushes +0.0 onto the x87 register stack.MnemonicOpcodeFLDZDescriptionD9 EEPush zero onto the x87 register stack.Related InstructionsFLD, FLD1, FLDPI, FLDL2T, FLDL2E, FLDLG2, FLDLN2rFLAGS AffectedNonex87 Condition Codex87 Condition CodeValueC0UDescription0No x87 stack fault occurred.1x87 stack overflow, if an x87 register stack fault was detected.C1C2UC3UNote: A flag set to 1 or cleared to 0 is M (modified).
Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE) withstack fault (SF)XInstruction ReferenceXXAn x87 stack overflow occurred.FLDZ275AMD64 Technology26569—Rev.
3.08—July 2007FMULFMULPFIMULFloating-Point MultiplyMultiplies the value in a floating-point register by the value in a memory location or another stackregister and stores the result in the first register. The instruction converts a single-precision or doubleprecision value in memory to double-extended-precision format before multiplying.If one operand is specified, the instruction multiplies the value in the ST(0) register by the value in thespecified memory location and stores the result in the ST(0) register.If two operands are specified, the instruction multiplies the value in the ST(0) register by the value inanother specified floating-point register and stores the result in the register specified in the firstoperand.The FMULP instruction pops the x87 stack after storing the product. The no-operand version of theFMULP instruction multiplies the value in the ST(1) register by the value in the ST(0) register andstores the product in the ST(1) register.The FIMUL instruction converts a short-integer or word-integer value in memory to double-extendedprecision format, multiplies it by the value in ST(0), and stores the product in ST(0).MnemonicOpcodeDescriptionFMUL ST(0),ST(i)D8 C8+iReplace ST(0) with ST(0) ∗ ST(i).FMUL ST(i),ST(0)DC C8+iReplace ST(i) with ST(0) ∗ ST(i).FMUL mem32realD8 /1Replace ST(0) with mem32real ∗ ST(0).FMUL mem64realDC /1Replace ST(0) with mem64real ∗ ST(0).FMULPDE C9Replace ST(1) with ST(0) ∗ ST(1), and pop the x87 registerstack.FMULP ST(i),ST(0)DE C8+iReplace ST(i) with ST(0) ∗ ST(i), and pop the x87 registerstack.FIMUL mem16intDE /1Replace ST(0) with mem16int ∗ ST(0).FIMUL mem32intDA /1Replace ST(0) with mem32int ∗ ST(0).Related InstructionsNonerFLAGS AffectedNone276FMULxInstruction Reference26569—Rev.
3.08—July 2007AMD64 Technologyx87 Condition Codex87 Condition CodeValueC0UDescription0No precision exception occurred.0x87 stack underflow, if an x87 register stack fault was detected.0Result was rounded down, if a precision exception was detected.1Result was rounded up, if a precision exception was detected.C1C2UC3UNote: A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefined flags are U.ExceptionsVirtual8086 ProtectedExceptionRealCause of ExceptionDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limit or wasnon-canonical.General protection,#GPXXXA memory address exceeded a data segment limit or wasnon-canonical.XA null data segment was used to reference memory.Page fault, #PFXXA page fault resulted from the execution of the instruction.Alignment check,#ACXXAn unaligned memory reference was performed whilealignment checking was enabled.XXAn unmasked x87 floating-point exception was pending.x87 floating-pointexception pending,#MFXx87 Floating-Point Exception Generated, #MFXXXA source operand was an SNaN value or an unsupportedformat.XXX±infinity was multiplied by ±zero.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.Overflow exception(OE)XXXA rounded result was too large to fit into the format of thedestination operand.Invalid-operationexception (IE)Instruction ReferenceFMULx277AMD64 Technology26569—Rev.
3.08—July 2007Virtual8086 ProtectedExceptionRealUnderflow exception(UE)XXXA rounded result was too small to fit into the format of thedestination operand.Precision exception(PE)XXXA result could not be represented exactly in the destinationformat.278Cause of ExceptionFMULxInstruction Reference26569—Rev. 3.08—July 2007AMD64 TechnologyFNOPFloating-Point No OperationPerforms no operation. This instruction affects only the rIP register. It does not otherwise affect theprocessor context.MnemonicOpcodeFNOPDescriptionD9 D0Perform no operation.Related InstructionsFWAIT, NOPrFLAGS AffectedNonex87 Condition CodeNoneExceptionsVirtual8086 ProtectedExceptionRealDevice not available,#NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) was set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.Instruction ReferenceCause of ExceptionFNOP279AMD64 Technology26569—Rev.
3.08—July 2007FPATANFloating-Point Partial ArctangentComputes the arctangent of the ordinate (Y) in ST(1) divided by the abscissa (X) in ST(0), which is theangle in radians between the X axis and the radius vector from the origin to the point (X, Y). It thenstores the result in ST(1) and pops the x87 register stack. The resulting value has the same sign as theordinate value and a magnitude less than or equal to π.There is no restriction on the range of values that FPATAN can accept. Table 2-3 shows the resultsobtained when computing the arctangent of various classes of numbers, assuming that underflow doesnot occur:Table 2-3.Computing Arctangent of NumbersX (ST(0))Y (ST(1))–∞–Finite–0+0+Finite+∞NaN–∞–3π/4–π/2–π/2–π/2–π/2–π/4NaN–Finite–π–π to –π/2–π/2–π/2–π/2 to –0—0NaN–0–π–π–π–0–0—0NaN+0+π+π+π+0+0+0NaN+Finite+π+π to +π/2+π/2+π/2+π/2 to +0+0NaN+∞+3π/4+π/2+π/2+π/2+π/2+π/4NaNNaNNaNNaNNaNNaNNaNNaNNaNMnemonicOpcodeFPATAND9 F3DescriptionCompute arctan(ST(1)/ST(0)), store the result in ST(1), andpop the x87 register stack.Related InstructionsFCOS, FPTAN, FSIN, FSINCOSrFLAGS AffectedNone280FPATANInstruction Reference26569—Rev.
3.08—July 2007AMD64 Technologyx87 Condition Codex87 Condition CodeValueC0UDescription0No precision exception occurred.0x87 stack underflow, if an x87 register stack fault was detected.0Result was rounded down, if a precision exception was detected.1Result was rounded up, if a precision exception was detected.C1C2UC3UNote: A flag set to 1 or cleared to 0 is M (modified). Unaffected flags are blank. Undefined flags are U.ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionDevice notavailable, #NMXXXThe emulate bit (EM) or the task switch bit (TS) of thecontrol register (CR0) is set to 1.x87 floating-pointexception pending,#MFXXXAn unmasked x87 floating-point exception was pending.x87 Floating-Point Exception Generated, #MFInvalid-operationexception (IE)XXXA source operand was an SNaN value or an unsupportedformat.Invalid-operationexception (IE) withstack fault (SF)XXXAn x87 stack underflow occurred.Denormalizedoperand exception(DE)XXXA source operand was a denormal value.Underflow exception(UE)XXXA rounded result was too small to fit into the format of thedestination operand.Precision exception(PE)XXXA result could not be represented exactly in the destinationformat.Instruction ReferenceFPATAN281AMD64 Technology26569—Rev.
3.08—July 2007FPREMFloating-Point Partial RemainderComputes the exact remainder obtained by dividing the value in ST(0) by that in ST(1), and stores theresult in ST(0). It computes the remainder by an iterative subtract-and-shift long division algorithm inwhich one quotient bit is calculated in each iteration.If the exponent difference between ST(0) and ST(1) is less than 64, the instruction computes all integerbits of the quotient, guaranteeing that the remainder is less in magnitude than the divisor in ST(1). Ifthe exponent difference is equal to or greater than 64, it computes only the subset of integer quotientbits numbering between 32 and 63, returns a partial remainder, and sets the C2 condition code bit to 1.FPREM is supported for software that was written for early x87 coprocessors.
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