Volume 4 128-Bit Media Instructions (794098), страница 43
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3.09—July 2007AMD64 TechnologyPSRLWPacked Shift Right Logical WordsRight-shifts each of the packed 16-bit values in the first source operand by the number of bits specifiedin the second operand and writes each shifted value in the corresponding word of the destination (firstsource). The first source/destination and second source operands are:••an XMM register and another XMM register or 128-bit memory location, oran XMM register and an immediate byte value.The high-order bits that are emptied by the shift operation are cleared to 0. If the shift value is greaterthan 15, the destination is cleared to 0.The PSRLW instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodeDescriptionPSRLW xmm1, xmm2/mem12866 0F D1 /rRight-shifts packed words in an XMM register by theamount specified in the low 64 bits of an XMMregister or 128-bit memory location.PSRLW xmm, imm866 0F 71 /2 ibRight-shifts packed words in an XMM register by theamount specified in an immediate byte value.xmm1...xmm2/mem128...127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....012764 630.shift rightshift rightxmm...imm8...127 112 111 96 95 80 79 64 63 48 47 32 31 16 15.....07 0.shift rightshift rightpsrlw-128.epsInstruction ReferencePSRLW327AMD64 Technology26568—Rev.
3.09—July 2007Related InstructionsPSLLD, PSLLDQ, PSLLQ, PSLLW, PSRAD, PSRAW, PSRLD, PSRLDQ, PSRLQrFLAGS AffectedNoneMXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XXXA null data segment was used to reference memory.XXXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GP328PSRLWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPSUBBPacked Subtract BytesSubtracts each packed 8-bit integer value in the second source operand from the corresponding packed8-bit integer in the first source operand and writes the integer result of each subtraction in thecorresponding byte of the destination (first source). The first source/destination operand is an XMMregister and the second source operand is another XMM register or 128-bit memory location.This instruction operates on both signed and unsigned integers.
If the result overflows, the carry isignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 8 bits of eachresult are written in the destination.The PSUBB instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePSUBB xmm1,xmm2/mem128DescriptionSubtracts packed byte integer values in an XMM registeror 128-bit memory location from packed byte integervalues in another XMM register and writes the result inthe destination XMM register.66 0F F8 /rxmm1........xmm2/mem128......1270..............1270..............subtractsubtractpsubb-128.epsRelated InstructionsPSUBD, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBWrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferencePSUBB329AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX330PSUBBInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPSUBDPacked Subtract DoublewordsSubtracts each packed 32-bit integer value in the second source operand from the correspondingpacked 32-bit integer in the first source operand and writes the integer result of each subtraction in thecorresponding doubleword of the destination (first source).
The first source/destination operand is anXMM register and the second source operand is another XMM register or 128-bit memory location.The PSUBD instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePSUBD xmm1, xmm2/mem128DescriptionSubtracts packed 32-bit integer values in an XMMregister or 128-bit memory location from packed 32-bitinteger values in another XMM register and writes theresult in the destination XMM register.66 0F FA /rxmm1.12796 95xmm2/mem128.64 63.32 310.12796 9564 63.32 310.subtractsubtractpsubd-128.epsThis instruction operates on both signed and unsigned integers. If the result overflows, the carry isignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 32 bits of eachresult are written in the destination.Related InstructionsPSUBB, PSUBQ, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBWrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferencePSUBD331AMD64 Technology26568—Rev.
3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX332PSUBDInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPSUBQPacked Subtract QuadwordSubtracts each packed 64-bit integer value in the second source operand from the correspondingpacked 64-bit integer in the first source operand and writes the integer result of each subtraction in thecorresponding quadword of the destination (first source). The first source/destination and sourceoperands are an XMM register and another XMM register or 128-bit memory location.The PSUBQ instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePSUBQ xmm1,xmm2/mem12866 0F FB /rDescriptionSubtracts packed 64-bit integer values in an XMMregister or 128-bit memory location from packed 64-bitinteger values in another XMM register and writes theresult in the destination XMM register.xmm1127xmm2/mem12864 63012764 630subtractsubtractpsubq-128.epsThis instruction operates on both signed and unsigned integers. If the result overflows, the carry isignored (neither the overflow nor carry bit in rFLAGS is set), and only the low-order 64 bits of eachresult are written in the destination.Related InstructionsPSUBB, PSUBD, PSUBSB, PSUBSW, PSUBUSB, PSUBUSW, PSUBWrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferencePSUBQ333AMD64 Technology26568—Rev. 3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX334PSUBQInstruction Reference26568—Rev.
3.09—July 2007PSUBSBAMD64 TechnologyPacked Subtract Signed With Saturation BytesSubtracts each packed 8-bit signed integer value in the second source operand from the correspondingpacked 8-bit signed integer in the first source operand and writes the signed integer result of eachsubtraction in the corresponding byte of the destination (first source). The first source/destinationoperand is an XMM register and the second source operand is another XMM register or 128-bitmemory location.The PSUBSB instruction is an SSE2 instruction. The presence of this instruction set is indicated by aCPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePSUBSB xmm1, xmm2/mem128DescriptionSubtracts packed byte signed integer values in anXMM register or 128-bit memory location from packedbyte integer values in another XMM register and writesthe result in the destination XMM register.66 0F E8 /rxmm1........xmm2/mem128......1270..............1270..............subtractsaturatesubtractsaturatepsubsb-128.epsFor each packed value in the destination, if the value is larger than the largest signed 8-bit integer, it issaturated to 7Fh, and if the value is smaller than the smallest signed 8-bit integer, it is saturated to 80h.Related InstructionsPSUBB, PSUBD, PSUBQ, PSUBSW, PSUBUSB, PSUBUSW, PSUBWrFLAGS AffectedNoneMXCSR Flags AffectedNoneInstruction ReferencePSUBSB335AMD64 Technology26568—Rev.
3.09—July 2007ExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX336PSUBSBInstruction Reference26568—Rev.
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