Volume 4 128-Bit Media Instructions (794098), страница 45
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3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX344PSUBWInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPUNPCKHBWUnpack and Interleave High BytesUnpacks the high-order bytes from the first and second source operands and packs them intointerleaved bytes in the destination (first source). The low-order bytes of the source operands areignored. The first source/destination operand is an XMM register and the second source operand isanother XMM register or 128-bit memory location.If the second source operand is all 0s, the destination contains the bytes from the first source operandzero-extended to 16 bits. This operation is useful for expanding unsigned 8-bit values to unsigned 16bit operands for subsequent processing that requires higher precision.The PUNPCKHBW instruction is an SSE2 instruction. The presence of this instruction set is indicatedby a CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKHBW xmm1,xmm2/mem128DescriptionUnpacks the eight high-order bytes in an XMM registerand another XMM register or 128-bit memory locationand packs them into interleaved bytes in thedestination XMM register.66 0F 68 /rxmm1127xmm2/mem12864 63. ....copy0127.64 63. .copy.127..copy.......0.copy..64 63...0punpckhbw-128.epsRelated InstructionsP U N P C K H D Q , P U N P C K H Q D Q , P U N P C K H W D , P U N P C K L B W, P U N P C K L D Q ,PUNPCKLQDQ, PUNPCKLWDrFLAGS AffectedNoneInstruction ReferencePUNPCKHBW345AMD64 Technology26568—Rev.
3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX346PUNPCKHBWInstruction Reference26568—Rev.
3.09—July 2007PUNPCKHDQAMD64 TechnologyUnpack and Interleave High DoublewordsUnpacks the high-order doublewords from the first and second source operands and packs them intointerleaved doublewords in the destination (first source). The low-order doublewords of the sourceoperands are ignored. The first source/destination operand is an XMM register and the second sourceoperand is another XMM register or 128-bit memory location.If the second source operand is all 0s, the destination contains the doubleword(s) from the first sourceoperand zero-extended to 64 bits. This operation is useful for expanding unsigned 32-bit values tounsigned 64-bit operands for subsequent processing that requires higher precision.The PUNPCKHDQ instruction is an SSE2 instruction.
The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKHDQ xmm1,xmm2/mem128DescriptionUnpacks two high-order doublewords in an XMMregister and another XMM register or 128-bit memorylocation and packs them into interleaved doublewordsin the destination XMM register.66 0F 6A /rxmm112796 95copyxmm2/mem12864 630127copy12796 95copy96 9564 6364 630copy32 310punpckhdq-128.epsRelated InstructionsP U N P C K H B W, P U N P C K H Q D Q , P U N P C K H W D , P U N P C K L B W, P U N P C K L D Q ,PUNPCKLQDQ, PUNPCKLWDrFLAGS AffectedNoneInstruction ReferencePUNPCKHDQ347AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX348PUNPCKHDQInstruction Reference26568—Rev.
3.09—July 2007PUNPCKHQDQAMD64 TechnologyUnpack and Interleave High QuadwordsUnpacks the high-order quadwords from the first and second source operands and packs them intointerleaved quadwords in the destination (first source). The first source/destination is an XMMregister, and the second source operand is another XMM register or 128-bit memory location. The loworder quadwords of the source operands are ignored.If the second source operand is all 0s, the destination contains the quadword from the first sourceoperand zero-extended to 128 bits. This operation is useful for expanding unsigned 64-bit values tounsigned 128-bit operands for subsequent processing that requires higher precision.The PUNPCKHQDQ instruction is an SSE2 instruction. The presence of this instruction set isindicated by a CPUID feature bit.
(See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKHQDQ xmm1, xmm2/mem128DescriptionUnpacks high-order quadwords in an XMMregister and another XMM register or 128-bitmemory location and packs them intointerleaved quadwords in the destination XMMregister.66 0F 6D /rxmm1127xmm2/mem12864 630127copy64 630copy12764 630punpckhqdq.epsRelated InstructionsPUNPCKHBW, PUNPCKHDQ, PUNPCKHWD, PUNPCKLBW, PUNPCKLDQ, PUNPCKLQDQ,PUNPCKLWDrFLAGS AffectedNoneInstruction ReferencePUNPCKHQDQ349AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX350PUNPCKHQDQInstruction Reference26568—Rev.
3.09—July 2007AMD64 TechnologyPUNPCKHWDUnpack and Interleave High WordsUnpacks the high-order words from the first and second source operands and packs them intointerleaved words in the destination (first source). The low-order words of the source operands areignored. The first source/destination operand is an XMM register and the second source operand isanother XMM register or 128-bit memory location.If the second source operand is all 0s, the destination contains the words from the first source operandzero-extended to 32 bits.
This operation is useful for expanding unsigned 16-bit values to unsigned 32bit operands for subsequent processing that requires higher precision.The PUNPCKHWD instruction is an SSE2 instruction. The presence of this instruction set is indicatedby a CPUID feature bit. (See “CPUID” in Volume 3.)MnemonicOpcodePUNPCKHWD xmm1,xmm2/mem128DescriptionUnpacks four high-order words in an XMM registerand another XMM register or 128-bit memorylocation and packs them into interleaved words inthe destination XMM register.66 0F 69 /rxmm1xmm2/mem128127 112 111 96 95 80 79 64 63.0127 112 111 96 95 80 79 64 63.copy.copy.copy...0copy..
111. 96. 95. 80. 79. 64 63 48. 47. 32. 31. 16. 15.127 1120punpckhwd-128.epsRelated InstructionsPUNPCKHBW, PUNPCKHDQ, PUNPCKHQDQ, PUNPCKLBW, PUNPCKLDQ, PUNPCKLQDQ,PUNPCKLWDrFLAGS AffectedNoneInstruction ReferencePUNPCKHWD351AMD64 Technology26568—Rev. 3.09—July 2007MXCSR Flags AffectedNoneExceptionsExceptionRealVirtual8086 ProtectedCause of ExceptionXXXThe SSE2 instructions are not supported, asindicated by EDX bit 26 of CPUID function0000_0001h.XXXThe emulate bit (EM) of CR0 was set to 1.XXXThe operating-system FXSAVE/FXRSTOR supportbit (OSFXSR) of CR4 is cleared to 0.Device not available,#NMXXXThe task-switch bit (TS) of CR0 was set to 1.Stack, #SSXXXA memory address exceeded the stack segment limitor was non-canonical.XXXA memory address exceeded a data segment limit orwas non-canonical.XA null data segment was used to reference memory.XXThe memory operand was not aligned on a 16-byteboundary while MXCSR.MM was cleared to 0.Page fault, #PFXXA page fault resulted from the execution of theinstruction.Alignment check, #ACXXAn unaligned memory reference was performed whilealignment checking was enabled withMXCSR.MM set to 1.Invalid opcode, #UDGeneral protection, #GPX352PUNPCKHWDInstruction Reference26568—Rev.
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